| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
 PDF version | |
| Home > Debug > Cache debug |
There are several memory system requirements for a debugger to work optimally on the cached processor:
if the debugger performs a memory access while in debug state, caches must not change their state unless the access is a write that hits in the cache
if the debugger performs a memory access while in debug state so that the cache state becomes incoherent with memory while in normal state, then one of the following conditions must be true:
the memory system detects this situation and performs some implicit operations that keep the cache coherent
the processor guarantees that the debugger can restore coherency after the memory access.
the means to keep cache coherency must be sufficient so that it does not significantly slow down the debugging process
a way to profile cache usage must be available.
| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
| PDF version | |
| Home > Debug > Cache debug |