Cortex™-A8 Technical Reference Manual 12.4.16. Watchpoint Control Registers

Cortex™-A8 Technical Reference Manual

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12.4.16. Watchpoint Control Registers

The WCRs contain the necessary control bits for setting:

watchpoints
linked watchpoints.

Figure 12.13 shows the bit arrangement of the Watchpoint Control Registers.

Figure 12.13. Watchpoint Control Registers format

Table 12.26 shows how the bit values correspond with the Watchpoint Control Registers functions.

Table 12.26. Watchpoint Control Registers bit functions

Bits	Field	Function
[31:29]	-	RAZ on reads, SBZP on writes.
[28:24]	Watchpoint address mask	Watchpoint address mask. This field is used to watch a range of addresses by masking lower order address bits out of the watchpoint comparison. b00000 = no mask b00001 = reserved b00010 = reserved b00011 = `0x00000007` mask for data address b00100 = `0x0000000F` mask for data address b00101 = `0x0000001F` mask for data address ... b11111 = `0x7FFFFFFF` mask for data address. Note If WCR[28:24] is not set to b00000, then WCR[12:5] must be set to b11111111. Otherwise, the behavior is Unpredictable. If WCR[28:24] is not set to b00000, then the corresponding WVR bits that are not being included in the comparison Should Be Zero. Otherwise, the behavior is Unpredictable. To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a debugger sets WCR[28:24] to b00111, and WCR[12:5] to b11111111. This is compatible with both ARMv7 debug compliant implementations that have an eight-bit WCR[12:5] and with those that have a four-bit WCR[8:5] byte address select field.
[23:21]	-	RAZ on reads, SBZP on writes.
[20]	E	Enable linking bit: 0 = linking disabled 1 = linking enabled. When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP field.
[19:16]	Linked BRP	Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is Unpredictable whether a watchpoint debug event is generated.
[15:14]	Secure state access control	Secure state access control. This field enables the watchpoint to be conditioned on the security state of the processor. b00 = watchpoint matches in both Secure and Nonsecure state b01 = watchpoint only matches in Nonsecure state b10 = watchpoint only matches in Secure state b11 = reserved.
[13]	-	RAZ on reads, SBZP on writes.
[12:5]	Byte address select	Byte address select. The WVR is programmed with word-aligned address. You can use this field to program the watchpoint so it only hits if certain byte addresses are accessed. For word-aligned addresses, WVRn[2]=1 indicates a 32-bit aligned address: b00000000 = the watchpoint never hits b0000xxx1 = the watchpoint hits if the byte at address (WVR & `0xFFFFFFFC`)+0 is accessed b0000xx1x = the watchpoint hits if the byte at address (WVR & `0xFFFFFFFC`)+1 is accessed b0000x1xx = the watchpoint hits if the byte at address (WVR & `0xFFFFFFFC`)+2 is accessed b00001xxx = the watchpoint hits if the byte at address (WVR & `0xFFFFFFFC`)+3 is accessed bxxx1xxxx = UNPREDICTABLE bxx1xxxxx = UNPREDICTABLE bx1xxxxxx = UNPREDICTABLE b1xxxxxxx = UNPREDICTABLE For double word-aligned addresses, WVRn[2]=0 indicates a 64-bit aligned address: b00000000 = the watchpoint never hits bxxxxxxx1 = the watchpoint hits if the byte at address (WVR & `0xFFFFFFFC`) +0 is accessed bxxxxxx1x = the watchpoint hits if the byte at address (WVR & `0xFFFFFFFC`) +1 is accessed bxxxxx1xx = the watchpoint hits if the byte at address (WVR & `0xFFFFFFFC`) +2 is accessed bxxxx1xxx = the watchpoint hits if the byte at address (WVR & `0xFFFFFFFC`) +3 is accessed bxxx1xxxx = the watchpoint hits if the byte at address (WVR & `0xFFFFFFF8`) +4 is accessed bxx1xxxxx = the watchpoint hits if the byte at address (WVR & `0xFFFFFFF8`) +5 is accessed bx1xxxxxx = the watchpoint hits if the byte at address (WVR & `0xFFFFFFF8`) +6 is accessed b1xxxxxxx = the watchpoint hits if the byte at address (WVR & `0xFFFFFFF8`) +7 is accessed.
[4:3]	L/S	Load/store access. The watchpoint can be conditioned to the type of access being done. b00 = reserved b01 = load, load exclusive, or swap b10 = store, store exclusive or swap b11 = either. SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local monitor within the processor.^[1]
[2:1]	S	Privileged access control. The watchpoint can be conditioned to the privilege of the access being done: b00 = reserved b01 = privileged, match if the processor does a privileged access to memory b10 = User, match only on nonprivileged accesses b11 = either, match all accesses. Note For all cases, the match refers to the privilege of the access, not the mode of the processor.
[0]	W	Watchpoint enable: 0 = watchpoint disabled, reset value 1 = watchpoint enabled.
^[1]A store exclusive that fails the local monitor will not cause a translation table walk, MMU fault, or watchpoint, see Store-exclusive instruction.

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