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The purpose of the USER ENable (USEREN) Register is to enable User mode to have access to the Performance Monitor Registers.
USEREN Register does not provide access to the registers that control interrupt generation.
The USEREN Register is:
a read/write register common to Secure and Nonsecure states
writable only in privileged mode and readable in any processor mode.
Figure 3.45 shows the bit arrangement of the USEREN Register.
Table 3.101 shows how the bit values correspond with the USEREN Register functions.
Table 3.101. User Enable Register bit functions
| Bits | Field | Function |
|---|---|---|
| [31:1] | - | RAZ on reads, SBZP on writes |
| [0] | EN | User mode enable |
Table 3.102 shows the results of attempted access for each mode.
Table 3.102. Results of access to the User Enable Register
Secure privileged | Nonsecure privileged | Secure User | Nonsecure User | |||||
|---|---|---|---|---|---|---|---|---|
| Read | Write | Read | Write | Read | Write | Read | Write | |
| EN = 0 | Data | Data | Data | Data | Data | Undefined exception | Data | Undefined exception |
| EN = 1 | Data | Data | Data | Data | Data | Undefined exception | Data | Undefined exception |
To access the USEREN Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c14, 0 ; Read USEREN Register
MCR p15, 0, <Rd>, c9, c14, 0 ; Write USEREN Register
| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
| PDF version | |
| Home > System Control Coprocessor > System control coprocessor registers > c9, User Enable Register |