R

R/W

[15]

Force ETM clock

R

Forces ETM clock enable active:

0 = does not prevent the processor clock generator from stopping the ETM clock, reset value

1 = prevents the processor clock generator from stopping the ETM clock.

[14]

Force NEON clock

R

R/W

Forces NEON clock enable active:

0 = does not prevent the processor clock generator from stopping the NEON clock, reset value

1 = prevents the processor clock generator from stopping the NEON clock.

[13]

Force main clock

R

R/W

Forces the main processor clock enable active:

0 = does not prevent the processor clock generator from stopping the main clock, reset value

1 = prevents the processor clock generator from stopping the main clock.

[12]

Force NEON single issue

R

R/W

Forces single issue of NEON instructions:

0 = does not force single issue of NEON instructions, reset value

1 = forces single issue of NEON instructions.

[11]

Force load/store single issue

R

R/W

Forces single issue of load/store instructions:

0 = does not force single issue of load/store instructions, reset value

1 = forces single issue of load/store instructions.

[10]

Force single issue

R

R/W

Forces single issue of all instructions:

0 = does not force single issue of all instructions, reset value

1 = forces single issue of all instructions.

[9]

R

R/W

Executes PLD instructions as a NOP instruction:

0 = PLD instructions behave as defined in the ARM Architecture Reference Manual, reset value

1 = PLD instructions are executed as NOP instructions.

The PLD instruction acts as a hint to the memory system. If the PLDNOP is set to 0, the processor performs a memory access for the PLD instruction. If the PLDNOP is set to 1, the processor does not perform a memory access. See the ARM Architecture Reference Manual for more information on the PLD instruction.

[8]

R

R/W

Executes WFI instructions as a NOP instruction:

0 = executes WFI instructions as defined in the ARM Architecture Reference Manual, reset value

1 = executes WFI instructions as NOP instruction.

The WFI instruction places the processor in a low-power state and stops it from executing further until an interrupt or a debug request occurs. If the WFINOP is set to 0, then the WFI instruction places the processor in a low-power state. If the WFINOP is set to 1, the WFI instruction is executed as a NOP and does not place the processor in a low-power state. See the ARM Architecture Reference Manual for more information on the WFI instruction.

[7]

R

R/W

Prevents BTB branch size mispredicts:

0 = enables BTB branch size mispredicts, reset value

1 = executes the CP15 Invalidate All and Invalidate by MVA instructions as specified and prevents BTB branch size mispredicts.

[6]

IBE

R

R/W

Invalidates BTB enable:

0 = executes the CP15 Invalidate All and Invalidate by MVA instructions as a NOP instruction, reset value

1 = executes the CP15 Invalidate All and Invalidate by MVA instructions as specified.

[5]

L1NEON

R

R/W

Enables caching NEON data within the L1 data cache:

0 = disables caching NEON data within the L1 data cache, reset value

1 = enables caching NEON data within the L1 data and L2 cache.

[4]

ASA

R

R/W

Enables speculative accesses on AXI:

0 = disables speculative accesses, reset value

1 = enables speculative accesses.

[3]

L1PE

R

R/W

Enables L1 cache parity detection:

0 = L1 cache parity disabled for both instruction and data caches, reset value

1 = L1 cache parity enabled.

[2]

-

R

R/W

UNP on reads, SBZ on writes.

[1]

L2EN

B

Enables L2 cache:

0 = L2 cache disabled

1 = L2 cache enabled. See Table 3.49 for details.

[0]

L1ALIAS

R

R/W

Enables L1 data cache hardware alias checks:

0 = L1 data cache hardware alias support enabled, reset value

1 = L1 data cache hardware alias support disabled.

Data

Data

Data

Banked Data

Undefined exception

Undefined exception

Undefined exception

Undefined exception