Cortex™-A8 Technical Reference Manual 3.2.54. c9, Interrupt Enable Clear Register

3.2.54. c9, Interrupt Enable Clear Register

The purpose of the INTerrupt ENable Clear (INTENC) Register is to determine if any of the Performance Monitor Count Registers, PMCNT0-PMCNT3 and CCNT, generate an interrupt on overflow.

The INTENC Register is:

a read/write register common to Secure and Nonsecure states
accessible in privileged mode only.

When reading this register, any interrupt overflow enable bit that reads as 0 indicates the interrupt overflow flag is disabled. Any interrupt overflow enable bit that reads as 1 indicates the interrupt overflow flag is enabled.

When writing this register, any interrupt overflow enable bit written with a value of 0 is ignored, that is, not updated. Any interrupt overflow enable bit written with a value of 1 clears the interrupt overflow enable bit.

Figure 3.47 shows the bit arrangement of the INTENC Register.

Figure 3.47. Interrupt Enable Clear Register format

Table 3.105 shows how the bit values correspond with the INTENC Register functions.

Table 3.105. Interrupt Enable Clear Register bit functions

Bits	Field	Function
[31]	C	CCNT overflow interrupt enable
[30:4]	-	UNP on reads, SBZP on writes
[3]	P3	PMCNT3 overflow interrupt enable
[2]	P2	PMCNT2 overflow interrupt enable
[1]	P1	PMCNT1 overflow interrupt enable
[0]	P0	PMCNT0 overflow interrupt enable

Table 3.106 shows the results of attempted access for each mode.

Table 3.106. Results of access to the Interrupt Enable Clear Register

	Secure privileged		Nonsecure privileged		Secure User		Nonsecure User
	Read	Write	Read	Write	Read	Write	Read	Write
EN = 0	Data	Data	Data	Data	Undefined exception	Undefined exception	Undefined exception	Undefined exception
EN = 1	Data	Data	Data	Data	Undefined exception	Undefined exception	Undefined exception	Undefined exception

To access the INTENC Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c14, 2 ; Read INTENC Register

MCR p15, 0, <Rd>, c9, c14, 2 ; Write INTENC Register

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