Cortex™-A8 Technical Reference Manual 3.2.36. c5, Data Fault Status Register

3.2.36. c5, Data Fault Status Register

The purpose of the Data Fault Status Register is to hold the source of the last data fault.

The Data Fault Status Register is:

a read/write register banked for Secure and Nonsecure states
accessible in privileged modes only.

Figure 3.30 shows the bit arrangement of the Data Fault Status Register when the data abort is not imprecise. When the data abort is imprecise, only bits [3:0] are valid.

Figure 3.30. Data Fault Status Register format

Table 3.69 shows how the bit values correspond with the Data Fault Status Register functions.

Table 3.69. Data Fault Status Register bit functions

Bits	Field	Function
[31:13]	-	UNP on reads, SBZ on writes.
[12]	SD	Indicates whether an AXI Decode or Slave error caused an abort. This bit is only valid for external aborts. For all other aborts this bit Should Be Zero: 0 = AXI Decode error caused the abort, reset value 1 = AXI Slave error caused the abort.
[11]	RW	Indicates whether a read or write access caused an abort: 0 = read access caused the abort, reset value 1 = write access caused the abort.
[10]	S	Part of the Status field. See bits [3:0] in this table. The reset value is 0.
[9:8]	-	RAZ on reads and ignore writes.
[7:4]	Domain	Indicates which one of the 16 domains, D15-D0, is accessed when a data fault occurs. This field takes values 0-15.
[3:0]	Status	Indicates the type of exception generated. To determine the data fault, bits [12] and [10] must be used in conjunction with bits [3:0]. The following encodings are in priority order, 1 is the highest: 0b000001 alignment fault 0b000100 instruction cache maintenance fault 0bx01100 L1 translation, precise external abort 0bx01110 L2 translation, precise external abort 0b011100 L1 translation precise parity error 0b011110 L2 translation precise parity error 0b000101 translation fault, section 0b000111 translation fault, page 0b000011 access flag fault, section 0b000110 access flag fault, page 0b001001 domain fault, section 0b001011 domain fault, page 0b001101 permission fault, section 0b001111 permission fault, page 0bx01000 precise external abort, nontranslation 0bx10110 imprecise external abort 0b011000 imprecise error, parity or ECC 0b000010 debug event. Any unused encoding not listed is reserved. Where x represents bit [12] in the encoding, bit [12] can be either: 0 = AXI Decode error caused the abort, reset value 1 = AXI Slave error caused the abort.

Note

When the SCR EA bit is set, see c1, Secure Configuration Register, the processor writes to the Secure Data Fault Status Register on a Monitor entry caused by an external abort.

To access the Data Fault Status Register, read or write CP15 with:

MRC p15, 0, <Rd>, c5, c0, 0 ; Read Data Fault Status Register

MCR p15, 0, <Rd>, c5, c0, 0 ; Write Data Fault Status Register

Copyright © 2006 ARM Limited. All rights reserved.	ARM DDI 0344B
Non-Confidential
PDF version