Cortex™-A8 Technical Reference Manual 3.2.46. c9, Overflow Flag Status Register

3.2.46. c9, Overflow Flag Status Register

The purpose of the Overflow Flag Status (FLAG) Register is to enable or disable any of the performance monitor counters producing an overflow flag.

When reading this register, any overflow flag that reads as 0 indicates the counter has not overflowed. Any overflow flag that reads as 1 indicates the counter has overflowed.

When writing this register, any overflow flag written with a value of 0 is ignored, that is, not updated. Any overflow flag written with a value of 1 clears the counter overflow flag.

The FLAG Register is:

a read/write register common to Secure and Nonsecure states
accessible as determined by c9, User Enable Register.

Figure 3.41 shows the bit arrangement of the FLAG Register.

Figure 3.41. Overflow Flag Status Register format

Table 3.89 shows how the bit values correspond with the FLAG Register functions.

Table 3.89. Overflow Flag Status Register bit functions

Bits	Field	Function
[31]	C	Cycle counter overflow flag
[30:4]	-	UNP on reads, SBZP on writes
[3]	P3	Counter 3 overflow flag
[2]	P2	Counter 2 overflow flag
[1]	P1	Counter 1 overflow flag
[0]	P0	Counter 0 overflow flag

Table 3.90 shows the results of attempted access for each mode.

Table 3.90. Results of access to the Overflow Flag Status Register

	Secure privileged		Nonsecure privileged		Secure User		Nonsecure User
	Read	Write	Read	Write	Read	Write	Read	Write
EN = 0^[1]	Data	Data	Data	Data	Undefined exception	Undefined exception	Undefined exception	Undefined exception
EN = 1	Data	Data	Data	Data	Data	Data	Data	Data
^[1]The EN bit in c9, User Enable Register enables User mode access of the Performance Monitor Registers.

To access the FLAG Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 3 ; Read FLAG Register

MCR p15, 0, <Rd>, c9, c12, 3 ; Write FLAG Register

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