Cortex™-A8 Technical Reference Manual 17.3. ETM ATB and CTI interfaces

Cortex™-A8 Technical Reference Manual

Revision: r1p1

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17.3. ETM ATB and CTI interfaces

Table 17.3 shows the setup and hold times for:

the ETM APB interface
the CTI.

Table 17.3. Timing parameters of ETM ATB and CTI interfaces

Signal	Clock	Setup parameter	Percent of clock period	Hold parameter	Percent of clock period
AFREADYM	ATCLK	T_ovafreadym	30%	T_ohafreadym	10%
AFVALIDM	ATCLK	T_isafvalidm	30%	T_ihafvalidm	10%
ASICCTL[7:0]	CLK	T_ovasicctl	30%	T_ohasicctl	10%
ATRESETn	ATCLK^[1]	T_isatresetn	50%	T_ihatresetn	10%
ATCLKEN	ATCLK	T_isatclken	30%	T_ihatclken	10%
ATREADYM	ATCLK	T_isatreadym	30%	T_ihatreadym	10%
ATBYTESM[1:0]	ATCLK	T_ovatbytesm	30%	T_ohatbytesm	10%
ATDATAM[31:0]	ATCLK	T_ovatdatam	30%	T_ohatdatam	10%
ATIDM[6:0]	ATCLK	T_ovatidm	30%	T_ohatidm	10%
ATVALIDM	ATCLK	T_ovatvalidm	30%	T_ohatvalidm	10%
TRIGGER	ATCLK	T_ovtrigger	30%	T_ohtrigger	10%
CTICHOUT[3:0]	ATCLK	T_ovctichout	30%	T_ohctichout	10%
CTICHIN[3:0]	ATCLK	T_isctichin	30%	T_ihctichin	10%
nCTIIRQ	CLK^[2]	T_ovnctiirq	30%	T_ohnctiirq	10%
^[1]This signal has multiple end-points and must be level-sensitive. ^[2]This signal has multiple end-points and must be treated as level-sensitive.

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