Cortex™-A8 Technical Reference Manual 17.5. L1 and L2 MBIST interfaces

Cortex™-A8 Technical Reference Manual

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17.5. L1 and L2 MBIST interfaces

Table 17.5 shows the setup and hold times for the L1 and L2 interfaces

Table 17.5. Timing parameters of the L1 and L2 MBIST interface

Signal	Clock	Setup parameter	Percent of clock period	Hold parameter	Percent of clock period
MBISTDATAINL1	CLK	T_{ismbistdatainl1}	30%	T_{ihmbistdatainl1}	5%
MBISTDSHIFTL1	CLK	T_{ismbistdshiftl1}	30%	T_{ihmbistdshiftl1}	5%
MBISTMODEL1	CLK	T_{ismbistmodel1}	30%	T_{ihmbistmodel1}	5%
MBISTRUNL1	CLK	T_ismbistrunl1	30%	T_ihmbistrunl1	5%
MBISTSHIFTL1	CLK	T_{ismbistshiftl1}	30%	T_{ihmbistshiftl1}	5%
MBISTRESULTL1[2:0]	CLK	T_{ovmbistresultl1}	30%	T_{ihmbistresultl1}	5%
MBISTDATAINL2	CLK	T_{ismbistdatainl2}	30%	T_{ihmbistdatainl2}	5%
MBISTDSHIFTL2	CLK	T_{ismbistdshiftl2}	30%	T_{ihmbistdshiftl2}	5%
MBISTMODEL2	CLK	T_{ismbistmodel2}	30%	T_{ihmbistmodel2}	5%
MBISTRUNL2	CLK	T_ismbistrunl2	30%	T_ihmbistrunl2	5%
MBISTSHIFTL2	CLK	T_{ismbistshiftl2}	30%	T_{ihmbistshiftl2}	5%
MBISTRESULTL2[2:0]	CLK	T_{ovmbistresultl2}	30%	T_{ohmbistresultl2}	5%
MBISTUSERINL2[18:0]	CLK	T_{ismbistuserinl2}	30%	T_{ihmbistuserinl2}	5%
MBISTUSEROUTL2[4:0]	CLK	T_{ovmbistuseroutl2}	50%	T_{ohmbistuseroutl2}	5%

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