Cortex™-A8 Technical Reference ManualRevision: r1p1
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A.3.2. DFT pins and additional MBIST pin requirements during MBIST testing

Table A.4 shows the signals necessary for DFT. It also shows the additional pins required during MBIST testing.

Table A.4. DFT and additional MBIST pin requirements

SignalI/OValue during functional modeValue during MBIST modeDescription

MBISTMODEL1

I01Configures L1 for MBIST mode and disables instruction fetch after reset.

MBISTMODEL2

I01Configures L2 for MBIST mode and disables instruction fetch after reset.
TESTMODEI00Indicates ATPG test mode. Deassert during MBISTMODE.
TESTCGATEI01Controls core clock gating during TESTMODE or MBISTMODE.
TESTEGATEI00Controls ETM clock gating. Deassert to save power during MBISTMODE.
TESTNGATEI00Controls NEON clock gating. Deassert to save power during MBISTMODE.
SEI00Scan enable signal. Ensures safe shifting of scan chains.
SAFESHIFTRAMI00Deactivates the RAM clocks for scan shifting.
SERIALTESTI00Concatenates the wrapper boundary register scan cells into a single scan chain.
SHIFTWRI00IEEE 1500 standard shift signal.
CAPTUREWRI00IEEE 1500 standard capture signal.
WINTESTI00Enables internal testing during ATPG.
WEXTESTI00Enables external testing during ATPG.
WSEI00Wrapper scan enable. Enables serial shifting of the wrapper scan chain.
PRESETnI-0Active-LOW APB reset input.
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