Cortex™-A8 Technical Reference ManualRevision: r1p1
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1.7. Configurable options

This section describes the configurable options for the processor.

Table 1.1 shows the L1 RAM size configurable options.

Table 1.1. L1 RAM size configurable options

FeatureRange of options

L1 cache size

16KB or 32KB

Table 1.2 shows the L2 RAM size configurable options.

Table 1.2. L2 RAM size configurable options

L2 cache sizeL2 tag bank

0KB

-

64KB

1 or 2

128KB

1 or 2

256KB

2

512KB

2 or 4

1MB

2 or 4

2MB

4

Table 1.3 shows the L2 parity and ECC configurable options.

Table 1.3. L2 RAM size configurable options

FeatureRange of options
L2 Parity/ECCYes or No

Table 1.4 shows the ETM and NEON configurable options.

Table 1.4. ETM and NEON configurable options

FeatureRange of options
ETMYes or No
NeonYes or No

Note

When you configure the processor without the NEON options, all attempted NEON and VFP instructions result in an Undefined exception.

Table 1.5 shows the AXI configurable options.

Table 1.5. AXI configurable options

FeatureRange of options

AXI bus width

64-bit or 128-bit

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