| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
 PDF version | |
| Home > NEON & VFPLite Programmer’s Model > About the NEON and VFPLite programmer’s model > NEON media coprocessor |
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| Home > NEON & VFPLite Programmer’s Model > About the NEON and VFPLite programmer’s model > NEON media coprocessor | |||
The NEON coprocessor is the ARM Single Instruction Multiple Data (SIMD) media processing architecture. It is part of ARMv7-A. The components of the NEON coprocessor are:
NEON register file with 32x64-bit general-purpose registers
NEON integer execute pipeline (ALU, Shift, MAC)
NEON dual, single-precision floating-point execute pipeline (FADD, FMUL)
NEON load/store and permute pipeline
nonpipelined VFP coprocessor that implements VFPv3 data-processing floating-point operations.
The NEON coprocessor can receive up to two valid NEON instructions per cycle from the ARM integer instruction execute unit. NEON load data can be retrieved from either the L1 data cache or the L2 memory system. In addition, it can receive 32-bit MCR data from or send 32-bit MRC data to the ARM integer instruction execute unit.
| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
| PDF version | |
| Home > NEON & VFPLite Programmer’s Model > About the NEON and VFPLite programmer’s model > NEON media coprocessor |