Cortex™-A8 Technical Reference ManualRevision: r1p1
Home > Memory Management Unit > MMU software-accessible registers

6.7. MMU software-accessible registers

Table 6.1 shows the CP15 registers that control the MMU. See Chapter 3 System Control Coprocessor for more information on CP15.

Table 6.1. CP15 register functions

Register

Cross reference
TLB Type Registerc0, TLB Type Register

Control Register

c1, Control Register

Nonsecure Access Control Registerc1, Nonsecure Access Control Register

Translation Table Base Register 0

c2, Translation Table Base Register 0

Translation Table Base Register 1

c2, Translation Table Base Register 1

Translation Table Base Control Register

c2, Translation Table Base Control Register

Domain Access Control Register

c3, Domain Access Control Register

Data Fault Status Register (DFSR)

c5, Data Fault Status Register

Instruction Fault Status Register (IFSR)

c5, Instruction Fault Status Register

Data Fault Address Register (DFAR)

c6, Data Fault Address Register

Instruction Fault Address Register (IFAR)

c6, Instruction Fault Address Register

TLB operations

c8, TLB operations

TLB Lockdown Registersc10, TLB Lockdown Registers
Primary Region Remap Registerc10, Memory Region Remap Registers
Normal Memory Remap Registerc10, Memory Region Remap Registers

FCSE PID Register

c13, FCSE PID Register

Context ID Register

c13, Context ID Register

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0344B
Non-Confidential
PDF file icon  PDF version
Home > Memory Management Unit > MMU software-accessible registers