Cortex™-A8 Technical Reference Manual 2.14.5. The GE[3:0] bits

Some of the SIMD instructions set GE[3:0] as greater than or equal bits for individual halfwords or bytes of the result, as Table 2.10 shows.

Table 2.10. GE[3:0] settings

	GE[3]	GE[2]	GE[1]	GE[0]
Instruction	A op B >= C	A op B >= C	A op B >= C	A op B >= C
Signed
SADD16	[31:16] + [31:16] ≥ 0	[31:16] + [31:16] ≥ 0	[15:0] + [15:0] ≥ 0	[15:0] + [15:0] ≥ 0
SSUB16	[31:16] - [31:16] ≥ 0	[31:16] - [31:16] ≥ 0	[15:0] - [15:0] ≥ 0	[15:0] - [15:0] ≥ 0
SADDSUBX	[31:16] + [15:0] ≥ 0	[31:16] + [15:0] ≥ 0	[15:0] - [31:16] ≥ 0	[15:0] - [31:16] ≥ 0
SSUBADDX	[31:16] - [15:0] ≥ 0	[31:16] - [15:0] ≥ 0	[15:0] + [31:16] ≥ 0	[15:0] + [31:16] ≥ 0
SADD8	[31:24] + [31:24] ≥ 0	[23:16] + [23:16] ≥ 0	[15:8] + [15:8] ≥ 0	[7:0] + [7:0] ≥ 0
SSUB8	[31:24] - [31:24] ≥ 0	[23:16] - [23:16] ≥ 0	[15:8] - [15:8] ≥ 0	[7:0] - [7:0] ≥ 0
Unsigned
UADD16	[31:16] + [31:16] ≥ 2¹⁶	[31:16] + [31:16] ≥ 2¹⁶	[15:0] + [15:0] ≥ 2¹⁶	[15:0] + [15:0] ≥ 2¹⁶
USUB16	[31:16] - [31:16] ≥ 0	[31:16] - [31:16] ≥ 0	[15:0] - [15:0] ≥ 0	[15:0] - [15:0] ≥ 0
UADDSUBX	[31:16] + [15:0] ≥ 2¹⁶	[31:16] + [15:0] ≥ 2¹⁶	[15:0] - [31:16] ≥ 0	[15:0] - [31:16] ≥ 0
USUBADDX	[31:16] - [15:0] ≥ 0	[31:16] - [15:0] ≥ 0	[15:0] + [31:16] ≥ 2¹⁶	[15:0] + [31:16] ≥2¹⁶
UADD8	[31:24] + [31:24] ≥ 2⁸	[23:16] + [23:16] ≥ 2⁸	[15:8] + [15:8] ≥ 2⁸	[7:0] + [7:0] ≥ 2⁸
USUB8	[31:24] - [31:24] ≥ 0	[23:16] - [23:16] ≥ 0	[15:8] - [15:8] ≥ 0	[7:0] - [7:0] ≥ 0

GE bit is 1 if A op B ≥ C, otherwise 0.

The SEL instruction uses GE[3:0] to select which source register supplies each byte of its result.

For unsigned operations, the usual ARM rules determine the GE bits for carries out of unsigned additions and subtractions, and so are carry-out bits.
For signed operations, the rules for setting the GE bits are chosen so that they have the same sort of greater than or equal functionality as for unsigned operations.

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