| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
 PDF version | |
| Home > NEON & VFPLite Programmer’s Model > General-purpose registers > VFPLite views of the register bank |
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| Home > NEON & VFPLite Programmer’s Model > General-purpose registers > VFPLite views of the register bank | |||
In VFPLite, you can view the register bank as:
Thirty-two 64-bit
doubleword registers, D0-D31. This view is also
available in NEON.
Thirty-two 32-bit single word registers, S0-S31.
Only half of the register bank is accessible in this view.
A combination of registers from the above views.
The mapping between the registers is as follows:
S<2n> maps
to the least significant half of D<n>
S<2n+1> maps to the most significant
half of D<n>
D<2n> maps to the least significant
half of Q<n>
D<2n+1> maps to the most significant
half of Q<n>.
For example, you can access the least significant half of
the elements of a vector in Q6 by referring to D12,
and the most significant half of the elements by referring to D13.
| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
| PDF version | |
| Home > NEON & VFPLite Programmer’s Model > General-purpose registers > VFPLite views of the register bank |