The AXI bus interface is the main interface to the system bus. It performs L2 cache fills and noncacheable accesses for both instructions and data. The AXI interface supports 64-bit or 128-bit wide input and output data buses. It also supports multiple outstanding requests on the AXI bus. The AXI signals are synchronous to the CLK input. A wide range of bus clock to core clock ratios is possible through the use of the AXI clock enable signal ACLKEN. See the AMBA AXI Protocol Specification for more information.