The purpose of the Secure or Nonsecure Vector Base Address Register is to hold the base address for exception vectors in the Secure and Nonsecure states. See Exceptions for more information.

The Secure or Nonsecure Vector Base Address Register is:

Figure 3.61 shows the bit arrangement of the Secure or Nonsecure Vector Base Address Register.

Table 3.136 shows how the bit values correspond with the Secure or Nonsecure Vector Base Address Register functions.

When an exception occurs in the Secure state, the core branches to address:

Secure Vector_Base_Address + Exception_Vector_Address.

When an exception occurs in the Nonsecure state, the core branches to address:

Nonsecure Vector_Base_Address + Exception_Vector_Address.

When high vectors are enabled, regardless of the value of the register the processor branches to 0xFFFF0000 + Exception_Vector_Address.

You can configure IRQ, FIQ, and external abort exceptions to branch to Monitor mode, see c1, Secure Configuration Register. In this case, the processor uses the Monitor Vector Base Address, see c12, Monitor Vector Base Address Register, to calculate the branch address. The Reset exception always branches to 0x00000000, regardless of the value of the Vector Base Address except when the processor uses high vectors.

Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception, see Data formats for the cache operations.

Table 3.137 shows the results of attempted access for each mode.

To access the Secure or Nonsecure Vector Base Address Register, read or write CP15 with:

MRC p15, 0, <Rd>, c12, c0, 0 ; Read Secure or Nonsecure Vector Base

                             ; Address Register

MCR p15, 0, <Rd>, c12, c0, 0 ; Write Secure or Nonsecure Vector Base

                             ; Address Register