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The tables in this section use the same format presented in Instruction-specific scheduling for ARM instructions and can be interpreted in the same way. The one difference between tables in this section and those in the Instruction-specific scheduling for ARM instructions is that the execution pipeline consists of stages N1-N6 instead of E1-E5.
Advanced SIMD data-processing instructions are divided into the following subcategories:
integer ALU instructions
integer multiply instructions
integer shift instructions
floating-point add instructions
floating-point multiply instructions.
Advanced SIMD load/store permute instructions are divided into the following subcategories:
byte permute instructions
load/store instructions
register transfer instructions.
This document uses the older assembler language instruction mnemonics. See Appendix B Instruction Mnemonics for information about the Unified Assembler Language (UAL) equivalents of the Advanced SIMD instruction mnemonics. See the ARM Architecture Reference Manual for more information on the UAL syntax.
| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
| PDF version | |
| Home > Instruction Cycle Timing > Instruction-specific scheduling for Advanced SIMD instructions |