| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
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| Home > Level 2 Memory System > About the L2 memory system |
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The processor contains an on-chip L2 memory system that consists of the following components:
L2 PreLoad Engine (PLE)
AXI interface
configurable L2 RAM.
The L2 memory system is tightly coupled to the L1 data cache and L1 instruction cache. The L2 memory system does not support hardware cache coherency, therefore software intervention is required to maintain coherency in the system.
The key features of the L2 memory system include:
configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB
fixed line length of 64 bytes
physically indexed and tagged
8-way set associative cache structure
support for lockdown format C
configurable 64-bit or 128-bit wide AXI system bus interface with support for multiple outstanding requests
random replacement policy
optional ECC or parity protection on the data RAM
optional parity protection on the tag RAM
MBIST
support for hardware reset of the L2 unified cache valid RAM, see Hardware RAM array reset.
| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
| PDF version | |
| Home > Level 2 Memory System > About the L2 memory system |