Cortex™-A8 Technical Reference Manual 3.2.40. c7, cache operations

3.2.40. c7, cache operations

The purpose of c7 is to manage the associated cache levels. The maintenance operations are formed into two management groups:

Set and way:
- clean
- invalidate
- clean and invalidate.
MVA:
- clean
- invalidate
- clean and invalidate.

In addition, the maintenance operations use the following definitions:

Point of coherency: The time when the imposition of any more cache becomes transparent for instruction, data, and translation table walk accesses to that address by any processor in the system.
Point of unification: The time when the instruction and data caches, and the TLB translation table walks have merged for a uniprocessor system.

Note

Reading from c7, except for reads from the Physical Address Register (PAR), causes an Undefined Instruction exception.
All accesses to c7 can only be executed in a privileged mode of operation, except Data Synchronization Barrier, Flush Prefetch Buffer, and Data Memory Barrier. These can be executed in User mode. Attempting to execute a privileged instruction in User mode results in an Undefined Instruction exception.
For information on the behavior of the invalidate, clean, and prefetch operations in the secure and nonsecure operations, see the ARM Architecture Reference Manual.

Data formats for the cache operations

The possible formats for the data supplied to the cache maintenance and prefetch buffer operations depend on the specific operation:

Table 3.73 shows the data value supplied to each cache maintenance and prefetch buffer operations.

Table 3.73. Register c7 cache and prefetch buffer maintenance operations

CRm	Opcode_2	Function	Data
c5	0	Invalidate all instruction caches to PoU. Also flushes branch target cache.^[1]	SBZ
c5	1	Invalidate instruction cache line by MVA to PoU.	MVA
c5	4	Prefetch flush. The prefetch buffer is flushed.^[2]	SBZ
c5	6	Invalidate entire branch predictor array.	SBZ
c5	7	Invalidate MVA from branch predictor array	MVA
c6	1	Invalidate Data or Unified cache line by MVA to PoU.	MVA
c6	2	Invalidate Data or Unified cache line by Set/Way.	Set/Way
c10	1	Clean Data or Unified cache line by MVA to PoC.	MVA
c10	2	Clean Data or Unified cache line by Set/Way.	Set/Way
c11	1	Clean Data or Unified cache line by MVA to PoU.	MVA
c14	1	Clean and Invalidate Data or Unified cache line by MVA to PoC.	MVA
c14	2	Clean and Invalidate Data or Unified cache line by Set/Way.	Set/Way
^[1]Only applies to separate instruction caches, does not apply to unified caches. ^[2]Available in User mode.

Set and way

Figure 3.32 shows the set and way format for invalidate and clean operations.

Figure 3.32. c7 format for set and way

Table 3.74 shows how the bit values correspond with the Cache Operation functions for set and way format operations.

Table 3.74. Functional bits of c7 for set and way

Bits	Field	Function
[31:32-A]	Way	Selects the way for the c7 set and way cache operation.
[31-A:L+S]	-	Reserved, SBZ.
[L+S-1:L]	Set	Selects the set for the c7 set and way cache operation.
[L-1:4]	-	Reserved, SBZ.
[3:1]	Level	Selects the cache level for the c7 set and way operation. 0 indicates cache level 1 is selected.
[0]	-	Reserved, SBZ.

For the processor, the L1 and L2 cache are configurable at implementation time. Therefore, the set and way fields are unique to the configured cache sizes. Table 3.75 shows the values of A, L, and S for L1 cache sizes, and Table 3.76 shows the values of A, L, and S for L2 cache sizes.

Table 3.75. Values of A, L, and S for L1 cache sizes

L1	A L S	Way	Set	Level
16KB	2 6 6	[31:30]	[11:6]	[3:1]
32KB	2 6 7	[31:30]	[12:6]	[3:1]

Table 3.76 shows the values of A, L, and S for L2 cache sizes and the resultant bit range for Way, Set, and Level. See Table 3.74 and Figure 3.32.

Table 3.76. Values of A, L, and S for L2 cache sizes

L2	A L S	Way	Set	Level
0KB	3 6 0	[31:29]	-	[3:1]
128KB	3 6 8	[31:29]	[13:6]	[3:1]
256KB	3 6 9	[31:29]	[14:6]	[3:1]
512KB	3 6 10	[31:29]	[15:6]	[3:1]
1024KB	3 6 11	[31:29]	[16:6]	[3:1]

See c0, Cache Type Register for more information on cache sizes.

MVA

Figure 3.33 shows the MVA format for invalidate, clean, and prefetch operations.

Figure 3.33. c7 format for MVA

Table 3.77 shows how the bit values correspond with the Cache Operation functions for MVA format operations.

Table 3.77. Functional bits of c7 for MVA

Bits	Field	Function
[31:6]	Modified virtual address	Specifies address to invalidate, clean, or prefetch
[5:0]	-	Reserved, SBZ

SBZ

The value supplied Should-Be-Zero. The value 0x00000000 must be written to the register.

VA to PA translation operations

The purpose of the VA to PA translation operations, nonsecure operations, is to provide a secure means to determine address translation between the Secure and Nonsecure states. VA to PA translations operate through:

PA Register

The purpose of the Physical Address Register (PAR) is to hold:

the Physical Address (PA) after a successful translation
the source of the abort for an unsuccessful translation.

Table 3.78 shows the purpose of the bits of the PAR for successful translations and Table 3.79 shows the purpose of the bits of the PAR for unsuccessful translations.

The PAR is:

a read/write register banked in Secure and Nonsecure states
accessible in privileged modes only.

Figure 3.34 shows the bit arrangement of the PAR for successful translations.

Figure 3.34. PA Register format for successful translation

Figure 3.35 shows the bit arrangement of the PAR for unsuccessful translations.

Figure 3.35. PA Register format for unsuccessful translation

Table 3.78 shows how the bit values correspond with the PAR for a successful translation.

Table 3.78. PA Register for successful translation bit functions

Bits	Field	Function
[31:12]	PA	Contains the physical address after a successful translation.
[11:10]	-	Reserved. UNP, SBZ.
[9]	NS	Indicates the state of the NS attribute bit in the translation table: 0 = secure memory 1 = nonsecure memory.
[8]	P	Not used in the processor.
[7]	SH	Indicates shareable memory: 0 = nonshared 1 = shared.
[6:4]	INNER	Indicates the inner attributes from the translation table: b000 = noncacheable b001 = strongly ordered b010 = reserved b011 = device b100 = reserved b101 = inner write-back, allocate on write b110 = inner write-through, no allocate on write b111 = inner write-back, no allocate on write.
[3:2]	OUTER	Indicates the outer attributes from the translation table: b00 = noncacheable b01 = write-back, allocate on write b10 = write-through, no allocate on write b11 = write-back, no allocate on write.
[1]	Supersection	Indicates if the result is a supersection: 0 = page is not a supersection, that is, PAR [31:12] contains PA[31:12], regardless of the page size. 1 = page is part of a supersection: PAR[31:24] contains PA[31:24] PAR[23:16] contains b00000000 PAR[15:12] contains b0000. Note PA[23:12] is the same as VA[23:12] for supersections.
[0]	-	Indicates that the translation succeeded: 0 = translation successful.

Table 3.79 shows how the bit values correspond with the PAR for an unsuccessful translation.

Table 3.79. PA Register for unsuccessful translation bit functions

Bits	Field	Function
[31:7]	-	Reserved. UNP, SBZ.
[6:1]	FSR[12,10,3:0]	Holds the FSR bits for the aborted address. See c5, Data Fault Status Register and c5, Auxiliary Fault Status Registers.
[0]	-	Indicates that the translation aborted: 1 = translation aborted.

Bits

Field

Function

[31:7]

Reserved. UNP, SBZ.

[6:1]

FSR[12,10,3:0]

Holds the FSR bits for the aborted address. See c5, Data Fault Status Register and c5, Auxiliary Fault Status Registers.

[0]

Indicates that the translation aborted:

1 = translation aborted.

Attempts to access the PAR in User mode results in an Undefined Instruction exception.

Note

The VA to PA translation can only generate an abort to the core if the operation failed because an external abort occurred on the possible translation table request. In this case, the processor does not update the PA Register. The processor updates the Data Fault Status Register and the Fault Address Register:

if the EA bit in the Secure Configuration Register is set to 1, the secure versions of the two registers are updated and the processor traps the abort into Monitor mode
if the EA bit in the Secure Configuration Register is not set to 1, the processor updates the secure or nonsecure versions of the two registers, depends whether the core is in Secure or Nonsecure state when the operation was issued.

For all other cases when the VA to PA operation fails, the processor only updates the PA Register, secure or nonsecure version, depends whether the core is in Secure or Nonsecure state when the operation was issued, with the Fault Status Register encoding and bit [0] set to 1. The Data Fault Status Register and Fault Address Register remain unchanged and the processor does not send an abort to the core.

To access the PA Register, read or write CP15 c7 with:

MRC p15, 0, <Rd>, c7, c4, 0 ; Read PA Register

MCR p15, 0, <Rd>, c7, c4, 0 ; Write PA Register

VA to PA translation in the current Secure or Nonsecure state

The purpose of the VA to PA translation in the current Secure or Nonsecure state is to translate the address with the current virtual mapping for either Secure or Nonsecure state.

The VA to PA translation in the current Secure or Nonsecure state use:

CP15 c7
four, write-only operations common to the Secure and Nonsecure states
operations accessible in privileged modes only.

The operations work for privileged or User access permissions and returns information in the PA Register for aborts, when the translation is unsuccessful, or translation table information, when the translation succeeds.

Attempts to access the VA to PA translation operations in the current Secure or Nonsecure state in User mode result in an Undefined Instruction exception.

To access the VA to PA translation in the current Secure or Nonsecure state, write CP15 c7 with:

MCR p15, 0, <Rn>, c7, c8, 3 ; get VA = <Rn> and run VA-to-PA translation

                            ; with User write permission.

                            ; if the selected translation table has the

                            ; User write permission, the PA is loaded in the PA

                            ; Register, otherwise abort information is loaded in

                            ; the PA Register.

MRC p15, 0, <Rd>, c7, c4, 0 ; read in <Rd> the PA value

Note

The VA that this operation uses is the true VA not the MVA.
General register <Rn> contains the VA for translation. The result returns in the PA Register.

VA to PA translation in the other Secure or Nonsecure state

The purpose of the VA to PA translation in the other Secure or Nonsecure state is to translate the address with the current virtual mapping in the Nonsecure state while the core is in the Secure state.

The VA to PA translation in the other Secure or Nonsecure state use:

CP15 c7
four, write-only operations in the Secure state only
operations accessible in privileged modes only.

The operations work in the Secure state for nonsecure privileged or nonsecure User access permissions and returns information in the PA Register for aborts, when the translation is unsuccessful, or translation table information, when the translation succeeds.

When a VA to PA translation occurs in the other state from the Secure state, the value of the NS bit for a successful translation is Unpredictable.

Attempts to access the VA to PA translation operations in the other Secure or Nonsecure state in any nonsecure or User mode result in an Undefined Instruction exception.

To access the VA to PA translation in the other Secure or Nonsecure state, write CP15 c7 with Opcode_2 set to:

4 for privileged read permission
5 for privileged write permission
6 for User read permission
7 for User write permission.

General register <Rn> contains the VA for translation. The result returns in the PA Register, for example:

MCR p15, 0, <Rn>, c7, c8, 4 ; get VA = <Rn> and run nonsecure translation

                            ; with nonsecure privileged read permission.

                            ; if the selected translation table has privileged

                            ; read permission, the PA is loaded in the PA

                            ; Register, otherwise abort information is loaded

                            ; in the PA Register.

MRC p15, 0, <Rd>, c7, c4, 0 ; read in <Rd> the PA value

Data synchronization barrier operation

The purpose of the data synchronization barrier operation is to ensure that all outstanding explicit memory transactions complete before any following instructions begin. This ensures that data in memory is up to date before the processor executes any more instructions.

The data synchronization barrier operation is:

a write-only operation, common to both Secure and Nonsecure states
accessible in both User and privileged modes.

Table 3.80 shows the results of attempted access for each mode.

Table 3.80. Results of access to the data synchronization barrier operation

Read	Write
Undefined Instruction exception	Data

To perform a data synchronization barrier operation, write CP15 with:

MCR p15, 0, <Rd>, c7, c10, 4 ; Data synchronization barrier operation

See the ARM Architecture Reference Manual for more information on memory barriers.

Data memory barrier operation

The purpose of the data memory barrier operation is to ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin. This ensures that data in memory is up to date for any memory transaction that depends on it.

The data memory barrier operation is:

a write-only operation, common to the Secure and Nonsecure states
accessible in User and privileged modes.

Table 3.81 shows the results of attempted access for each mode.

Table 3.81. Results of access to the data memory barrier operation

Read	Write
Undefined Instruction exception	Data

To perform a data memory barrier operation, write CP15 with:

MCR p15, 0, <Rd>; c7, c10, 5 ; Data memory barrier operation

See the ARM Architecture Reference Manual for more information on memory barriers.

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