ETMv3.3 permits a number of configurations. Table 14.1 shows the options implemented
in the Cortex-A8 ETM.
Table 14.1. ETM implementation
| Resource description | Configuration |
|---|
| Instruction trace | Yes |
| Data address trace | Yes |
| Data value trace | No |
| Jazelle trace | - |
| Address comparator pairs | 4 |
| Data comparators | 2 |
| Context ID comparators | 1 |
| Sequencer | Yes |
| Start/stop block | Yes |
| EmbeddedICE comparators | 0 |
| External inputs | 4 |
| External outputs | 2 |
| Extended external inputs | 49 |
| Extended external input selectors | 2 |
| Instrumentation resources | 4 |
| FIFOFULL | No |
| FIFOFULL level setting | N/A |
| Branch broadcasting | Yes |
| ASIC Control Register (bits) | 8 |
| Data suppression | Yes |
| Software access to registers | Memory |
| Readable registers | Yes |
| FIFO size | 128 bytes |
| Minimum port size | 32 |
| Maximum port size | 32 |
| Port modes | Dynamic |
| Asynchronous ATB interface | Yes |
| Load pc first | No |
| Fetch comparisons | No |
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