Cortex™-A8 Technical Reference Manual 3.1.1. System control coprocessor functional groups

3.1.1. System control coprocessor functional groups

The system control coprocessor is a set of registers that you can write to and read from. Some of the registers permit more than one type of operation. The functional groups for the registers are:

The system control coprocessor controls the Security Extensions operation of the processor:

some of the registers are only accessible in the Secure state
some of the registers are banked for Secure and Nonsecure states
some of the registers are common to Secure and Nonsecure states.

Note

When Monitor mode is active, the core is in the Secure state. The processor treats all accesses as secure and the system control coprocessor behaves as if it operates in the Secure state regardless of the value of the NS bit, see c1, Secure Configuration Register. In Monitor mode the NS bit defines which copies of the banked registers in the system control coprocessor the processor can access:

NS = 0: Access to Secure state CP15 registers.
NS = 1: Access to Nonsecure state CP15 registers.

Registers that are only accessible in the Secure state are always accessible in Monitor mode, regardless of the value of the NS bit.

Table 3.1 shows the overall functionality of the system control coprocessor registers.

Table 3.1. System control coprocessor register functions

Function	Register/operation	Reference to description
System control and configuration	Control	c1, Control Register
	Auxiliary Control	c1, Auxiliary Control Register
	Secure Configuration	c1, Secure Configuration Register
	Secure Debug Enable	c1, Secure Debug Enable Register
	Nonsecure Access Control	c1, Nonsecure Access Control Register
	Coprocessor Access Control	c1, Coprocessor Access Control Register
	Secure or Nonsecure Vector Base Address	c12, Secure or Nonsecure Vector Base Address Register
	Monitor Vector Base Address	c12, Monitor Vector Base Address Register
	Main ID Register^[1]	c0, Main ID Register
	Silicon ID Register	c0, Silicon ID Register
	Product Features	c0, Memory Model Feature Register 0 - c0, Instruction Set Attributes Registers 5-7
MMU control and configuration	TLB Type	c0, TLB Type Register
MMU control and configuration	Translation Table Base 0	c2, Translation Table Base Register 0
	Translation Table Base 1	c2, Translation Table Base Register 1
	Translation Table Base Control	c2, Translation Table Base Control Register
	Domain Access Control	c3, Domain Access Control Register
	Data Fault Status	c5, Data Fault Status Register
	Auxiliary Fault Status	c5, Auxiliary Fault Status Registers
	Instruction Fault Status	c6, Instruction Fault Address Register
	Instruction Fault Address	c6, Instruction Fault Address Register
	Data Fault Address	c6, Data Fault Address Register
	TLB Operations	c8, TLB operations
	Memory region remap	c10, Memory Region Remap Registers
	Context ID	c13, Context ID Register
	FCSE PID	c13, FCSE PID Register
	Thread and Process ID	c13, Thread and Process ID Registers
Cache control and configuration	Cache Type	c0, Cache Type Register
	Cache Level Identification	c0, Cache Level ID Register
	Cache Size Identification	c0, Cache Size Identification Registers
	Cache Size Selection	c0, Cache Size Selection Register
	Cache operations	c7, cache operations
L2 cache PreLoad Engine (PLE) control and configuration	PLE Identification and Status	c11, PLE Identification and Status Registers
	PLE User Accessibility	c11, PLE User Accessibility Register
	PLE Channel Number	c11, PLE Channel Number Register
	PLE Enable	c11, PLE enable commands
	PLE Control	c11, PLE Control Register
L2 cache PLE control and configuration	PLE Internal Start Address	c11, PLE Internal Start Address Register
	PLE Internal End Address	c11, PLE Internal End Address Register
	PLE Channel Status	c11, PLE Channel Status Register
	PLE Context ID	c11, PLE Context ID Register
L1 instruction and data cache, and TLB Debug	L1 Instruction and Data cache, BTB, GHB, and TLB Debug	c15, L1 system array debug data registers
L2 unified cache	L2 unified cache	c15, L2 system array debug data registers
System performance monitor	Performance monitoring	c9, Performance Monitor Control Register - c9, Interrupt Enable Clear Register
^[1]Returns device ID code.

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