The purpose of the L2 cache PLE control and configuration control registers is to:

Code can execute several PLE operations while in User mode if these operations are enabled by the PLE User Accessibility Register.

If the PLE control registers attempt to execute a privileged operation in User mode, the processor takes an Undefined instruction trap.

The PLE control registers operation specifies the block of data for transfer, the location of the transfer, and the direction of the PLE. See L2 PLE for more information on the operation.