Cortex™-A8 Technical Reference Manual 3.1.2. System control and configuration

3.1.2. System control and configuration

The purpose of the system control and configuration registers is to provide overall management of:

Security Extensions behavior
memory functionality
interrupt behavior
exception handling
program flow prediction
coprocessor access rights for CP0-CP13.

The system control and configuration registers also provide the processor ID. Some of the functionality depends on how you set external signals at reset.

System control and configuration behaves in three ways:

as a set of flags or enables for specific functionality
as a set of numbers, values that indicate system functionality
as a set of addresses for processes in memory.

Security Extensions write access disable

The processor supports a primary input pin, CP15SDISABLE, to disable write access to the CP15 registers.

When the CP15SDISABLE input is set to 1, any attempt to write to the secure version of the banked register, NS-bit is 0, or any non-banked register, NS-state is 0 results in an Undefined Instruction exception.

Changes in the pin on an instruction boundary occur as quickly as practically possible after a change to this pin. Software must perform a IMB after a change to this pin has occurred on the boundary of the macros to ensure that its effects are recognized on following instructions.

At reset, it is expected that this pin is set to logic 0 by the SoC hardware. Control of this pin is expected to remain within the SoC chip that implements the processor.

Table 3.2 shows the CP15 registers affected by the primary input pin, CP15SDISABLE.

Table 3.2. CP15 registers affected by CP15SDISABLE

Register	Instruction
Control Register	`MCR p15, 0, <Rd>, c1, c0, 0`
Translation Table Base 0	`MCR p15, 0, <Rd>, c2, c0, 0`
Translation Table Control Register	`MCR p15, 0, <Rd>, c2, c0, 2`
Domain Access Control	`MCR p15, 0, <Rd>, c3, c0, 0`
Primary Region Remap	`MCR p15, 0, <Rd>, c10, c2, 0`
Normal Memory Region Remap	`MCR p15, 0, <Rd>, c10, c2, 1`
Vector Base	`MCR p15, 0, <Rd>, c12, c0, 0`
Monitor Base	`MCR p15, 0, <Rd>, c12, c0, 1`
FCSE	`MCR p15, 0, <Rd>, c13, c0, 0`
Array operations	`MCR p15, 0, <Rd>, c15, c0-15, 0`-7 `MRC p15, 0, <Rd>, c15, c0-15, 0`-7

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