Cortex™-A8 Technical Reference Manual 12.5. Management registers

12.5. Management registers

The Management registers define the standardized set of registers that is implemented by all CoreSight components. These registers are described in this section.

Table 12.32 shows the contents of the Management registers for the debug unit.

Table 12.32. Management registers

Offset	Register number	Access	Mnemonic	Power domain	Description
`0xD00-0xDFC`	832-895	R	-	Debug	Processor Identifier Registers. See Processor ID Registers.
`0xE00-0xEF0`	854-956	R	-	-	RAZ.
`0xEF4`	957	RW	ITCTRL-IOC	Core	Integration Internal Output Control Register. See Integration Internal Output Control Register.
`0xEF8`	958	RW	ITCTRL-EOC	Core	Integration External Output Control Register. See Integration External Output Control Register.
`0xEFC`	959	R	ITCTRL-IS	Core	Integration Input Status Register. See Integration Input Status Register.
`0xF00`	960	RW	ITCTRL	Core	Integration Mode Control Register. See Integration Mode Control Register.
`0xF04-0xF9C`	961-999	R	-	Debug	RAZ, reserved for Management Register expansion.
`0xFA0`	1000	RW	CLAIMSET	Debug	Claim Tag Set Register. See Claim Tag Set Register.
`0xFA4`	1001	RW	CLAIMCLR	Debug	Claim Tag Clear Register. See Claim Tag Clear Register.
`0xFA8-0xFBC`	1002-1003	R	-	-	RAZ.
`0xFB0`	1004	W	LOCKACCESS	Debug	Lock Access Register. See Lock Access Register.
`0xFB4`	1005	R	LOCKSTATUS	Debug	Lock Status Register. See Lock Status Register.
`0xFB8`	1006	R	AUTHSTATUS	Debug	Authentication Status Register. See Authentication Status Register.
`0xFBC-0xFC4`	1007-1009	R	-	-	RAZ.
`0xFC8`	1010	R	DEVID	Debug	RAZ, reserved for Device Identifier.
`0xFCC`	1011	R	DEVTYPE	Debug	Device Type Register. See Device Type Register.
`0xFD0-0xFFC`	1012-1023	R	-	Debug	Identification Registers. See Identification Registers.

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