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The processor contains one CPSR, and six SPSRs for exception handlers to use. The program status registers:
hold information about the most recently performed logical or arithmetic operation
control the enabling and disabling of interrupts
set the processor operating mode.
Figure 2.12 shows the bit arrangements of the program status registers.
The bits identified in Figure 2.12 as Do Not Modify (DNM) must not be modified by software. These bits are:
Readable, to enable the processor state to be preserved, for example, during process context switches.
Writable, to enable the processor state to be restored. To maintain compatibility with future ARM processors, and as good practice, you are strongly advised to use a read-modify-write strategy when you change the CPSR.
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