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| Home > Programmer’s Model > Processor operating states | |||
The processor has the following operating states controlled by the T bit and J bit in the CPSR.
32-bit, word-aligned ARM instructions are executed in this state.
T bit is 0 and J bit is 0.
16-bit and 32-bit, halfword-aligned Thumb-2 instructions.
T bit is 1 and J bit is 0.
16-bit and 32-bit, halfword-aligned variant of the Thumb-2 instruction set designed as a target for dynamically generated code. This is code compiled on the device either shortly before or during execution from a portable bytecode or other intermediate or native representation.
T bit is 1 and J bit is 1.
The processor does not support Jazelle state. This means there is no processor state where the T bit is 0 and J bit is 1.
Transition between ARM and Thumb states does not affect the processor mode or the register contents. See the ARM Architecture Reference Manual for information on entering and exiting ThumbEE state.
| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
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