Cortex™-A8 Technical Reference Manual 3.2.71. c13, FCSE PID Register

3.2.71. c13, FCSE PID Register

The c13, Context ID Register replaces the FCSE PID Register. Use of the FCSE PID Register is deprecated.

The FCSE PID Register is:

a read/write register banked for Secure and Nonsecure states
accessible in privileged modes only.

Figure 3.64 shows the bit arrangement of the FCSE PID Register.

Figure 3.64. FCSE PID Register format

Table 3.142 shows how the bit values correspond with the FCSE PID Register functions.

Table 3.142. FCSE PID Register bit functions

Bits	Field	Function
[31:25]	FCSE PID	Holds the ProcID. Identifies a specific process for fast context switch. The reset value is 0. The purpose of the FCSE PID Register is to provide the ProcID for fast context switch memory mappings. The MMU uses the contents of this register to map memory addresses in the range 0-32MB.
[24:0]	-	Reserved. UNP, SBZP.

Bits

Field

Function

[31:25]

FCSE PID

Holds the ProcID. Identifies a specific process for fast context switch. The reset value is 0.

The purpose of the FCSE PID Register is to provide the ProcID for fast context switch memory mappings. The MMU uses the contents of this register to map memory addresses in the range 0-32MB.

[24:0]

Reserved. UNP, SBZP.

Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception, see Security Extensions write access disable.

Table 3.143 shows the results of attempted access for each mode.

Table 3.143. Results of access to the FCSE PID Register^[60]

Secure privileged		Nonsecure privileged		Secure User		Nonsecure User
Read	Write	Read	Write	Read	Write	Read	Write
Secure data	Secure data	Nonsecure data	Nonsecure data	Undefined	Undefined	Undefined	Undefined

To access the FCSE PID Register, read or write CP15 with:

MRC p15, 0, <Rd>, c13, c0, 0 ; Read FCSE PID Register

MCR p15, 0, <Rd>, c13, c0, 0 ; Write FCSE PID Register

To change the ProcID and perform a fast context switch, write to the FCSE PID Register. You are not required to flush the contents of the TLB after the switch because the TLB still holds the valid address tags.

Because a write to the FCSE PID Register causes a pipeline flush, the effect is immediate. The next executed instruction is fetched with the new PID.

Note

You must not rely on this behavior for future compatibility. An IMB must be executed between changing the ProcID and fetching from locations that are translated by the ProcID.

Addresses issued by the processor in the range 0-32MB are translated by the ProcID. Address A becomes A + (ProcID x 32MB). The MMU uses this translated address, the MVA. Addresses above 32MB are not translated. The ProcID is a 7-bit field, enabling 128 x 32MB processes to be mapped.

Note

If ProcID is 0, as it is on Reset, then there is a flat mapping between the processor and the MMU.

Figure 3.65 shows how addresses are mapped using the FCSE PID Register.

Figure 3.65. Address mapping with the FCSE PID Register

Copyright © 2006-2008 ARM Limited. All rights reserved.	ARM DDI 0344E
PDF version