Cortex™-A8 Technical Reference Manual 3.2.5. c0, TLB Type Register

The purpose of the TLB Type Register is to return the number of lockable entries for both the instruction and data TLBs.

Each TLB has 32 entries organized as fully associative and lockable TLB.

The TLB Type Register is:

Figure 3.3 shows the bit arrangement of the TLB Type Register.

Figure 3.3. TLB Type Register format

Table 3.9 shows how the bit values correspond with the TLB Type Register functions.

Table 3.9. TLB Type Register bit functions

Bits	Field	Function
[31:24]	-	Reserved, Read-As-Zero (RAZ).
[23:16]	ILsize	Instruction lockable size specifies the number of instruction TLB lockable entries: `0x20` = Processor has 32 lockable entries.
[15:8]	DLsize	Data lockable size specifies the number of unified or data TLB lockable entries: `0x20` = Processor has 32 lockable entries.
[7:1]	-	Reserved, RAZ.
[0]	U	Unified specifies if the TLB is unified or if there are separate instruction and data TLBs: `0x1` = Processor has separate instruction and data TLBs.

Table 3.10 shows the results of attempted access for each mode.

Table 3.10. Results of access to the TLB Type Register^[4]

Secure privileged		Nonsecure privileged		Secure User		Nonsecure User
Read	Write	Read	Write	Read	Write	Read	Write
Data	Undefined	Data	Undefined	Undefined	Undefined	Undefined	Undefined

To access the TLB Type Register, read CP15 with:

MRC p15, 0, <Rd>, c0, c0, 3  ; Read TLB Type Register

Copyright © 2006-2008 ARM Limited. All rights reserved.	ARM DDI 0344E
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