Cortex™-A8 Technical Reference Manual 3.2.64. c11, PLE Internal Start Address Register

3.2.64. c11, PLE Internal Start Address Register

The purpose of the PLE Internal Start Address Register for each channel is to define the start address, that is, the first address that data transfers go to or from.

The PLE Internal Start Address Register is:

a 32-bit read/write register with one register for each PLE channel common to Secure and Nonsecure states
accessible in User and privileged modes.

The PLE Internal Start Address Register bits [31:0] contain the Internal Start Virtual Address (VA). Figure 3.57 shows this format.

Figure 3.57. PLE Internal Start Address Register bit format

Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control Register. The processor can access this register in User mode if the U bit for the currently selected channel is set to 1, see c11, PLE User Accessibility Register.

Table 3.129 shows the results of attempted access for each mode.

Table 3.129. Results of access to the PLE Internal Start Address Register^[53]

		Secure privileged		Nonsecure privileged		Secure User		Nonsecure User
U bit	PLE bit	Read	Write	Read	Write	Read	Write	Read	Write
0	0	Data	Data	Undefined	Undefined	Undefined	Undefined	Undefined	Undefined
0	1	Data	Data	Data	Data	Undefined	Undefined	Undefined	Undefined
1	0	Data	Data	Undefined	Undefined	Data	Data	Undefined	Undefined
1	1	Data	Data	Data	Data	Data	Data	Data	Data

To access the PLE Internal Start Address Register, set the PLE Channel Number Register to the appropriate PLE channel and read or write CP15 c11 with:

MRC p15, 0, <Rd>, c11, c5, 0 ; Read PLE Internal Start Address Register

MCR p15, 0, <Rd>, c11, c5, 0 ; Write PLE Internal Start Address Register

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