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The purpose of the PLE Internal End Address Register for each channel is to define the number of cache lines transferred.
The PLE Internal End Address Register is:
a 32-bit read/write register with one register for each PLE channel common to Secure and Nonsecure states
accessible in User and privileged modes.
Figure 3.58 shows the bit arrangement of the PLE Internal End Address Register functions.
The PLE Internal End Address Register bits [N:6] contain the number of cache lines transferred where N is determined by the L2 cache size as defined in Table 3.130.
Table 3.130. Maximum transfer size for various L2 cache sizes
| Cache size | N | Maximum number of lines | Maximum transfer size |
|---|---|---|---|
| 0KB | 6 | 0 | 0KB[1] |
| 128KB | 14 | 256 | 16KB |
| 256KB | 15 | 512 | 32KB |
| 512KB | 16 | 1024 | 64KB |
| 1024KB | 17 | 2048 | 128KB |
[1] For a 0KB cache, the PLE setup code must read the Cache Size ID Register, see c0, Cache Size Identification Registers, before attempting PLE access. In a 0KB environment, the PLE does nothing. | |||
Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control Register. The processor can access this register in User mode if the U bit for the currently selected channel is set to 1, see c11, PLE User Accessibility Register.
Table 3.131 shows the results of attempted access for each mode.
Table 3.131. Results of access to the PLE Internal End Address Register[54]
| Secure privileged | Nonsecure privileged | Secure User | Nonsecure User | ||||||
|---|---|---|---|---|---|---|---|---|---|
| U bit | PLE bit | Read | Write | Read | Write | Read | Write | Read | Write |
| 0 | 0 | Data | Data | Undefined | Undefined | Undefined | Undefined | Undefined | Undefined |
| 1 | Data | Data | Data | Data | Undefined | Undefined | Undefined | Undefined | |
| 1 | 0 | Data | Data | Undefined | Undefined | Data | Data | Undefined | Undefined |
| 1 | Data | Data | Data | Data | Data | Data | Data | Data | |
To access the PLE Internal End Address Register, set the PLE Channel Number Register to the appropriate PLE channel and read or write CP15 with:
MRC p15, 0, <Rd>, c11, c7, 0 ; Read PLE Internal End Address Register
MCR p15, 0, <Rd>, c11, c7, 0 ; Write PLE Internal End Address Register
| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
| PDF version | |
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