Instructions that can be used to return from an exception

These instructions change the PC. They potentially change processor state, privilege mode, and security state. To fetch the target instructions in the new privilege mode, the pipeline must be flushed.

Instructions that restore the CPSR from memory or from the SPSR

These instructions change the PC. They potentially change processor state, privilege mode, and security state. To fetch the target instructions in the new privilege mode, the processor must flush the pipeline.

PC-destination data-processing instructions with immediate values in ARM state.

As described, PC-destination data-processing instructions where the second operand is an immediate, are not predicted

BXJ

The processor implements the trivial Jazelle extension, so BXJ becomes BX. This can be used as an unpredictable indirect branch instruction to force a pipeline flush on execution.

ENTERX/LEAVEX

Transitions between Thumb and ThumbEE state are not predicted.