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Cortex™-A8 Technical Reference ManualRevision: r2p2
Home > Introduction > Configurable options

1.7. Configurable options

Table 1.1 lists the configurable options for the Cortex-A8 processor.

Table 1.1. Cortex-A8 configurable options

FeatureOptions

AXI bus width

64-bit or 128-bit bus width

L1 RAM

L1 cache size:

  • 16KB

  • 32KB.

L2 RAM

L2 cache size:

  • 0KB

  • 128KB

  • 256KB

  • 512KB

  • 1MB.

L2 parity/ECCYes or No
ETMYes or No
NEON

Yes or No

Note

When you configure the processor without the NEON options, all attempted Advanced SIMD and VFP instructions result in an Undefined Instruction exception.

IEM

Support:

  • all power domains and retention

  • no power domain or retention

  • level-shifting only

  • debug PCLK, ETM CLK, and ETM ATCLK power domain

  • NEON power domain

  • L1 data RAMs and L2 RAMs retention

  • L2 RAMs retention.

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