Cortex™-A8 Technical Reference Manual 14.3. ETM register summary

14.3. ETM register summary

The ETM registers are defined in the ETM Architecture Specification.

Table 14.2 shows the values of the Identification registers and the Integration registers that are implementation-defined and are not described in the ETM Architecture Specification.

Table 14.2. ETM register summary

Register name	Base offset^[1]	Type	Reset value	Description
Configuration Code	`0x004`	R	`0x8D294024`	Configuration Code Register
ID	`0x1E4`	R	`0x410CF235`	ID Register
Configuration Code Extension	`0x1E8`	R	`0x000008A2`	Configuration Code Extension Register
ITMISCOUT	`0xEDC`	W	-	ITMISCOUT Register
ITMISCIN	`0xEE0`	R	-^[2]	ITMISCIN Register
ITTRIGGER	`0xEE8`	W	-	ITTRIGGER Register
ITATBDATA0	`0xEEC`	W	-	ITATBDATA0 Register
ITATBCTR2	`0xEF0`	R	-^b	ITATBCTR2 Register
ITATBCTR1	`0xEF4`	W	-	ITATBCTR1 Register
ITATBCTR0	`0xEF8`	W	-	ITATBCTR0 Register
PeripheralID4	`0xFD0`	R	`0x00000004`	Peripheral Identification Registers
PeripheralID5	`0xFD4`	R	`0x00000000`
PeripheralID6	`0xFD8`	R	`0x00000000`
PeripheralID7	`0xFDC`	R	`0x00000000`
PeripheralID0	`0xFE0`	R	`0x00000021`
PeripheralID1	`0xFE4`	R	`0x000000B9`
PeripheralID2	`0xFE8`	R	`0x0000005B`
PeripheralID3	`0xFEC`	R	`0x00000000`
ComponentID0	`0xFF0`	R	`0x0000000D`	Component Identification Registers
ComponentID1	`0xFF4`	R	`0x00000090`
ComponentID2	`0xFF8`	R	`0x00000005`
ComponentID3	`0xFFC`	R	`0x000000B1`
^[1]The value given in the Base offset column is the address offset for memory-mapped access. To get the register number used in the ETM Architecture Specification, divide this offset by four. ^[2]The values of these read-only registers depend on the signals on external pins of the ETM. Therefore it is not possible to define the register reset values.

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