Cortex™-A8 Technical Reference Manual 17.4. APB interface and miscellaneous debug signals

17.4. APB interface and miscellaneous debug signals

Table 17.4 shows the setup and hold times for:

the APB interface
the miscellaneous debug signals.

PCLK is the clock for the APB interface and some miscellaneous debug signals, and CLK is the clock for all other miscellaneous debug signals.

Table 17.4. Timing parameters of APB interface and miscellaneous debug signals

Signal	Clock	Setup parameter	Percent of clock period	Hold parameter
COMMRX^[1]	CLK	T_ovcommrx	30%	T_ohcommrx
COMMTX^[1]	CLK	T_ovcommtx	30%	T_ohcommtx
DBGACK	CLK	T_ovdbgack	30%	T_ohdbgack
DBGNOCLKSTOP	CLK	T_{isdbgnoclkstop}	30%	T_{ihdbgnoclkstop}
DBGROMADDR[31:12]^[2]	CLK	T_isdbgromaddr	30%	T_ihdbgromaddr
DBGROMADDRV^[2]	CLK	T_{isdbgromaddrv}	30%	T_{ihdbgromaddrv}
DBGSELFADDR[31:12]^[2]	CLK	T_{isdbgselfaddr}	30%	T_{ihdbgselfaddr}
DBGSELFADDRV^[2]	CLK	T_{isdbgselfaddrv}	30%	T_{ihdbgselfaddrv}
EDBGRQ^[1]	PCLK	-	-	-
DBGEN	PCLK	-	-	-
DBGOSLOCKINIT^[2]	PCLK	T_{isdbgoslockinit}	30%	T_{ihdbgoslockinit}
DBGNOPWRDWN^[1]	PCLK	T_{ovdbgnopwrdwn}	30%	T_{ohdbgnopwrdwn}
DBGPWRDWNREQ^[1]	PCLK	-	-	-
ETMPWRDWNREQ^[1]^,^[3]	PCLK	-	-	-
DBGPWRDWNACK	PCLK	T_{ovdbgpwrdwnack}	30%	T_{ohdbgpwrdwnack}
ETMPWRDWNACK^[3]	PCLK	T_{ovetmpwrdwnack}	30%	T_{ohetmpwrdwnack}
PRESETn^[1]^,^[4]	PCLK	-	-	-
PCLKEN	PCLK	T_ispclken	30%	T_ihpclken
PADDR31	PCLK	T_ispaddr31	30%	T_ihpaddr31
PADDR11TO2[11:2]	PCLK	T_ispaddr11to2	30%	T_ihpaddr11to2
PENABLE	PCLK	T_ispenable	30%	T_ihpenable
PSELCTI^[5]	PCLK	T_ispselcti	30%	T_ihpselcti
PSELDBG	PCLK	T_ispseldbg	30%	T_ihpseldbg
PSELETM^[4]	PCLK	T_ispseletm	30%	T_ihpseletm
PWRITE	PCLK	T_ispwrite	30%	T_ihpwrite
PRDATA[31:0]	PCLK	T_ovprdata	30%	T_ohprdata
PWDATA[31:0]	PCLK	T_ispwdata	30%	T_ihpwdata
PREADY	PCLK	T_ovpready	30%	T_ohpready
PSLVERR	PCLK	T_ovpslverr	30%	T_ohpslverr
NIDEN^[1]	PCLK	-	-	-
SPIDEN^[1]	PCLK	-	-	-
SPNIDEN^[1]	PCLK	-	-	-
^[1]This signal has multiple end-points and must be treated as level-sensitive. ^[2]This is a static input to the processor. ^[3]This signal is not required because debug and the ETM use the same power domain. ^[4]Figure 10.6 shows how this signal must be set up. ^[5]This signal is not present when the processor is configured without the ETM.

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