| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
 PDF version | |
| Home > System Control Coprocessor > About the system control coprocessor > Array debug |
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| Home > System Control Coprocessor > About the system control coprocessor > Array debug | |||
The purpose of array debug is to enable debug of the Cortex-A8 processor by accessing data, only in a secure state and privilege state, in the following arrays:
L1:
instruction and data cache data RAMs
instruction and data cache tag RAMs
TLB entries
branch predictor arrays.
L2 cache RAMs
parity error detection registers.
You can use the registers to observe the contents of the cache without executing a load or store instruction to debug:
frequency issues
Real Time Operating System (RTOS).
| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
| PDF version | |
| Home > System Control Coprocessor > About the system control coprocessor > Array debug |