Cortex™-A8 Technical Reference ManualRevision: r2p2
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17.3. ATB and CTI interfaces

Table 17.3 shows the setup and hold times for:

Table 17.3. Timing parameters of ATB and CTI interfaces

SignalClockSetup parameterPercent of clock periodHold parameter
AFREADYMATCLKTovafreadym30%Tohafreadym
AFVALIDMATCLKTisafvalidm30%Tihafvalidm
ASICCTL[7:0]CLKTovasicctl30%Tohasicctl
ATRESETn[1],[2]ATCLK---
ATCLKENATCLKTisatclken30%Tihatclken
ATREADYMATCLKTisatreadym30%Tihatreadym
ATBYTESM[1:0]ATCLKTovatbytesm30%Tohatbytesm
ATDATAM[31:0]ATCLKTovatdatam30%Tohatdatam
ATIDM[6:0]ATCLKTovatidm30%Tohatidm
ATVALIDMATCLKTovatvalidm30%Tohatvalidm
TRIGGERATCLKTovtrigger30%Tohtrigger
CTICHOUT[3:0]ATCLKTovctichout30%Tohctichout
CTICHIN[3:0]ATCLK---
nCTIIRQ[1]CLKTovnctiirq30%Tohnctiirq

[1] This signal has multiple end-points and must be treated as level-sensitive.

[2] Figure 10.6 shows how this signal must be set up.

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