| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
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The processor can accommodate many different levels of static, or leakage power management. All of these techniques are specific to a given implementation of the processor. Some possibilities that the processor can accommodate are:
full retention
power domains or islands such as integer core, ETM and debug, L2 RAM, and NEON
usage of multi-Vt such as high-Vt, standard-Vt, or low-Vt.
This technical reference manual does not document retention or the usage of multi-Vt. However, this manual describes the power domains, or islands that are supported and the methods that are required to manage those domains in a manner that has been validated within the processor.
To completely eliminate leakage power consumption in the processor, you must remove the power supplied to the processor. Before powering down, all architectural state must be saved to memory and the L1 data cache or L2 unified cache must be cleaned to the point of coherency. When powering up the processor, you must apply a complete reset sequence with software that restores the architectural state. The sequence takes significant time and energy to perform a full power-down of the processor.
To improve the response time of a power-down sequence, the processor supports several key features to minimize the response time and to reduce the leakage power consumption:
The processor enables the debug, ETM, and NEON units to be powered down while the rest of the processor is active.
The processor is designed so that the L1 data cache or L2 unified cache can retain state while the rest of the processor is powered down. This avoids the time and energy consuming process of cleaning the caches before powering down.
The processor enables the debug logic to remain powered up while the rest of the processor is powered down. This enables system debug to continue while the processor is powered down. All powered-down processor resources are not available to the debugger. As a result, the debug logic indicates an error to the debugger that the processor is in a powered-down state.
The processor supports many different power islands combinations, including a single monolithic power grid, resulting in a single power domain. The supported power domains are:
the NEON unit
all debug PCLK logic, ETM CLK logic, and ETM ATCLK logic
the L2 cache arrays
the L1 data cache arrays
all remaining logic within the processor, excluding the previous power domain, also known as the integer core.
Figure 10.11 shows the supported power domains.
When implementing the different power domains, the following modes of operation apply:
integer core in running mode:
All logic are powered and operational.
NEON are powered down and all other logic powered and operational. This mode minimizes the NEON leakage when NEON is not required.
Debug PCLK, ETM CLK, and ETM ATCLK are powered down and all other logic powered and operational. This mode minimizes the leakage of the debug and trace facilities when they are not required.
NEON, debug PCLK, ETM ATCLK, and ETM CLK are powered down, with all other logic powered and operational.
Integer core and NEON in powered down mode:
L1 data cache or L2 cache are powered up. This mode enables data to be retained in the L1 data cache or the L2 cache. This mode can greatly minimize the time and energy required to power down the processor.
Debug PCLK, ETM CLK, and ETM ATCLK are powered up. This mode enables the debug and trace external interfaces to remain active, enabling the debugger to detect that the processor is powered down.
L1 data cache or L2 cache, debug PCLK, ETM CLK, and ETM ATCLK are powered down.
If all power domains are implemented, the power domains can be independently controlled to give eight combinations of power-up and power-down domains. However, only some power-up and power-down domain combinations are valid. These are shown in Table 10.2.
Table 10.2. Valid power domains
| Integer core | Debug and ETM | NEON |
|---|---|---|
Powered down | Powered down | Powered down |
Powered down | Powered up | Powered down |
Powered up | Powered down | Powered down |
Powered up | Powered up | Powered down |
Powered up | Powered down | Powered up |
Powered up | Powered up | Powered up |
From the power domains shown in Figure 10.11, the following voltage domains can be derived. Figure 10.12 shows this.
The voltage domains represent the power supply distributions that might be required in the Cortex-A8 processor. These include:
Connects to SoC debug power domain.
Operates at the same voltage as the processor but exists in same power domain as debug.
Operates at the same voltage as the processor and can be powered down while the processor is running.
Supports retention in the L2 cache, and supports SRAM voltage.
Supports retention in the L1 data cache, and supports SRAM voltage.
Supports SRAM voltage.
All logic within the integer core, not including SRAMs.
Any or all of these voltage domains can be removed from the processor. However, the removal of those domains must comply with the supported power domain configurations listed in Table 10.2.
If NEON is not required, you can reduce leakage by turning off the power to the NEON unit. While the NEON unit is powered down, any Advanced SIMD instructions executed take the Undefined Instruction exception. The OS uses the Undefined Instruction exception on an Advanced SIMD instruction as a signal to apply power to the NEON unit, if powered down, or to activate NEON, if disabled.
To enable NEON to be powered down, the implementation must place NEON on a separately controlled power supply. In addition, the outputs of NEON must be clamped to benign values while NEON is powered down, to indicate that NEON is idle.
To power down the NEON power domain while the processor is in reset, apply the following sequence:
Assert both ARESETn and ARESETNEONn to place the processor in reset. You must assert ARESETn and ARESETNEONn for at least eight CLK cycles before activating the NEON clamps.
Activate the NEON output clamps by asserting the CLAMPNEONOUT input HIGH.
Remove power from the NEON power domain.
Deassert ARESETn, but continue to assert ARESETNEONn.
If the processor is executing a power-on reset sequence or is first powering up:
Assert both ARESETn and ARESETNEONn. You must assert ARESETn and ARESETNEONn for at least eight CLK cycles before activating the NEON clamps.
Activate the NEON output clamps by asserting the CLAMPNEONOUT input HIGH.
While keeping the NEON power domain off, supply power to the other active power domains.
Deassert ARESETn, but continue to assert ARESETNEONn.
While ARESETNEONn remains asserted, all Advanced SIMD instructions cause an Undefined Instruction exception.
If ARESETNEONn is deasserted or the NEON output clamps are released without following one of the specified NEON power-up sequences, the results are Unpredictable and might cause the processor to deadlock.
To power down the NEON power domain while the processor is not in reset, the NEON power domain must be placed into an idle state. Apply the following sequence to place the NEON power domain into an idle state:
Software must disable access to the NEON unit using the Coprocessor Access Control Register, see c1, Coprocessor Access Control Register. All outstanding Advanced SIMD instructions retire and all subsequent Advanced SIMD instruction cause an Undefined Instruction exception.
MRC p15, 0, <Rd>, c1, c0, 2; Read Coprocessor Access Control Register
BIC <Rd>, <Rd>, #0xF00000; Disable access to CP10 and CP11
MCR p15, 0, <Rd>, c1, c0, 2; Write Coprocessor Access Control Register
Software must signal to the external system that the NEON unit is disabled.
Assert ARESETNEONn to place NEON in reset. You must assert ARESETNEONn for at least eight CLK cycles before activating the NEON clamps.
Activate the NEON output clamps by asserting the CLAMPNEONOUT input HIGH.
Remove power from the NEON power domain.
If ARESETNEONn is deasserted or the NEON output clamps are released without following one of the specified NEON power-up sequences, the results are Unpredictable and might cause the processor to deadlock.
To apply power to the NEON power domain while the processor is in reset, use the following sequence:
Assert ARESETn and keep ARESETNEONn asserted.
Apply power to the NEON power domain.
Release the NEON output clamps by deasserting CLAMPNEONOUT.
Deassert ARESETn and ARESETNEONn.
After the completion of the reset sequence, you can enable the NEON unit using the Coprocessor Access Control Register. See c1, Coprocessor Access Control Register.
To apply power to the NEON power domain while the processor is not in reset, use the sequence that follows. With the NEON power domain currently powered down, it is assumed that ARESETNEONn is asserted.
Software must disable access to the NEON unit using the Coprocessor Access Control Register, see c1, Coprocessor Access Control Register.
MRC p15, 0, <Rd>, c1, c0, 2; Read Coprocessor Access Control Register
BIC <Rd>, <Rd>, #0xF00000; Disable access to CP10 and CP11
MCR p15, 0, <Rd>, c1, c0, 2; Write Coprocessor Access Control Register
Software must signal to the external system that it is safe to power up the NEON unit.
Apply power to the NEON power domain.
Deassert ARESETNEONn. NEON requires a minimum of 20 CLK cycles to complete its reset sequence. Therefore, the system must wait until NEON has completed its reset sequence before releasing the NEON clamps.
Release the NEON output clamps by deasserting CLAMPNEONOUT.
Software must poll the external system to determine that it is safe to enable the NEON unit.
After the completion of the reset sequence, you can enable the NEON unit using the Coprocessor Access Control Register. See c1, Coprocessor Access Control Register.
If the core is running in an environment where debug facilities are not required, you can reduce leakage power by powering down the debug PCLK, ETM CLK, and ETM ATCLK power domains. Debug PCLK, ETM CLK, and ETM ATCLK power domains must be built using a common power supply.
To power down the debug PCLK, ETM CLK, and ETM ATCLK power domains, the implementation must place debug PCLK, ETM CLK, and ETM ATCLK on a separately controlled and shared power supply. In addition, the outputs of debug PCLK, ETM CLK, and ETM ATCLK must be clamped to benign values while powered down to indicate that the interface is idle.
To power down the debug PCLK, ETM CLK, and ETM ATCLK power domains, apply the following sequence:
Assert both PRESETn and ATRESETn. You must assert PRESETn for at least eight PCLK cycles and ATRESETn for at least eight ATCLK cycles before asserting CLAMPDBGOUT.
Activate the debug PCLK, ETM CLK, and ETM ATCLK output clamps by asserting the CLAMPDBGOUT input HIGH.
Remove power from the debug PCLK, ETM CLK, and ETM ATCLK power domains. PRESETn and ATRESETn must remain asserted while the domain is powered down.
To power up the debug PCLK, ETM CLK, and ETM ATCLK power domains, use the sequence that follows. It is assumed that both PRESETn and ATRESETn are asserted during the sequence.
Apply power to the debug PCLK, ETM CLK, and ETM ATCLK power domains.
Release the debug PCLK, ETM CLK, and ETM ATCLK output clamps by deasserting CLAMPDBGOUT.
If the system uses the debug PCLK, ETM CLK, and ETM ATCLK hardware, it is safe to deassert either PRESETn, ATRESETn, or both.
| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
| PDF version | |
| Home > Clock, Reset, and Power Control > Power control > Static or leakage power management |