Cortex™-A8 Technical Reference Manual 17.2. AXI interface

17.2. AXI interface

Table 17.2 shows the setup and hold times for the AXI interface signals.

Table 17.2. Timing parameters of AXI interface

Signal	Clock	Setup parameter	Percent of clock period	Hold parameter
A64n128^[1]	CLK	-	-	-
ACLKEN	CLK	T_isaclken	30%	T_ihaclken
ARADDR[31:0]	CLK	T_ovaraddr	30%	T_oharaddr
ARBURST[1:0]	CLK	T_ovarburst	30%	T_oharburst
ARCACHE[3:0]	CLK	T_ovarcache	30%	T_oharcache
ARID[3:0]	CLK	T_ovarid	30%	T_oharid
ARLEN[3:0]	CLK	T_ovarlen	30%	T_oharlen
ARLOCK[1:0]	CLK	T_ovarlock	30%	T_oharlock
ARPROT[2:0]	CLK	T_ovarprot	30%	T_oharprot
ARSIZE[2:0]	CLK	T_ovarsize	30%	T_oharsize
ARVALID	CLK	T_ovarvalid	30%	T_oharvalid
ARREADY	CLK	T_isarready	30%	T_iharready
RDATA[127:0]	CLK	T_isrdata	30%	T_ihrdata
RID[3:0]	CLK	T_isrid	30%	T_ihrid
RLAST	CLK	T_isrlast	30%	T_ihrlast
RRESP[1:0]	CLK	T_isrresp	30%	T_ihrresp
RVALID	CLK	T_isrvalid	30%	T_ihrvalid
RREADY	CLK	T_ovrready	30%	T_ohrready
AWADDR[31:0]	CLK	T_ovawaddr	30%	T_ohawaddr
AWBURST[1:0]	CLK	T_ovawburst	30%	T_ohawburst
AWCACHE[3:0]	CLK	T_ovawcache	30%	T_ohawcache
AWID[3:0]	CLK	T_ovawid	30%	T_ohawid
AWLEN[3:0]	CLK	T_ovawlen	30%	T_ohawlen
AWLOCK[1:0]	CLK	T_ovawlock	30%	T_ohawlock
AWPROT[2:0]	CLK	T_ovawprot	30%	T_ohawprot
AWSIZE[2:0]	CLK	T_ovawsize	30%	T_ohawsize
AWVALID	CLK	T_ovawvalid	30%	T_ohawvalid
AWREADY	CLK	T_isawready	30%	T_ihawready
WDATA[127:0]	CLK	T_ovwdata	30%	T_ohwdata
WID[3:0]	CLK	T_ovwid	30%	T_ohwid
WLAST	CLK	T_ovwlast	30%	T_ohwlast
WSTRB[15:0]	CLK	T_ovwstrb	30%	T_ohwstrb
WVALID	CLK	T_ovwvalid	30%	T_ohwvalid
WREADY	CLK	T_iswready	30%	T_ihwready
BID[3:0]	CLK	T_isbid	30%	T_ihbid
BRESP[1:0]	CLK	T_isbresp	30%	T_ihbresp
BVALID	CLK	T_isbvalid	30%	T_ihbvalid
BREADY	CLK	T_ovbready	30%	T_ohbready
^[1]This is a static input to the processor.

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