Cortex™-A8 Technical Reference Manual 17.1. About setup and hold times

17.1. About setup and hold times

The setup and hold times of processor interface signals are necessary timing parameters for analyzing processor performance. This chapter specifies the setup and hold times of the processor interface signals.

The notation for setup and hold times of input signals is:

T_is: Input setup time. T_is is the amount of time the input data is valid before the next rising clock edge.
T_ih: Input hold time. T_ih is the amount of time the input data is valid after the next rising clock edge.

Figure 17.1 shows the setup and hold times of an input signal.

Figure 17.1. Input timing parameters

The time during which the processor can sample input data is Tissignal.

The notation for setup and hold times of output signals is:

T_ov: Output valid time. T_ov is the amount of time after the rising clock edge before valid output data appears.
T_oh: Output hold time. T_oh is the amount of time the output data is valid after the next rising clock edge.

Figure 17.2 shows the setup and hold times of an output signal.

Figure 17.2. Output timing parameters

The timing parameter tables in this chapter show setup and hold parameters of each signal as percentages of the relevant clock as shown in Table 17.1.

Table 17.1. Format of timing parameter tables

Signal	Clock	Setup parameter	Percent of clock period	Hold parameter
INPUT	CLK	T_isinput	50%	T_ihinput
OUTPUT	PCLK	T_ovoutput	30%	T_ohoutput

The setup parameter values are based on the Slow-Slow (SS) corner under the following conditions:

125 °C
V_DD = nominal operating voltage – 10%
target frequency = f_max.

The hold parameter values are based on the Fast-Fast (FF) corner under the following conditions:

-40 C
V_DD = nominal operating voltage + 10%
target frequency = f_max.

The nominal operating voltage for the process is defined to be V_dd.

Note

The hold time requirements for the macrocell I/O are not specified in this document. The hold time is specific to process and implementation requirements and therefore, are controlled by the implementor.

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