Cortex™-A8 Technical Reference ManualRevision: r2p2
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A.5. APB interface

Table A.6 shows the APB interface signals.

Table A.6. APB interface

SignalI/OResetDescription
PRESETnI-

Active-LOW APB reset input:

0 = reset APB

1 = do not reset APB.

PCLKI-APB clock.
PCLKENI-

APB clock enable:

0 = not enabled

1 = enabled.

PADDR31

I

-

APB address bus bit [31]:

0 = not an external debugger access

1 = external debugger access.

PADDR11TO2[11:2]I-APB address bus bits [11:2].
PENABLEI-

APB transfer complete flag:

0 = APB not in ENABLE cycle

1 = APB in ENABLE cycle.

PENABLE remains asserted for only one cycle.

PSELCTI[1]I-

CTI registers select:

0 = CTI registers not selected

1 = CTI registers selected.

PSELDBGI-

Debug registers select:

0 = debug registers not selected

1 = debug registers selected.

PSELETM[1]I-

ETM registers select:

0 = ETM registers not selected

1 = ETM registers selected.

PWRITEI-

APB read or write signal:

0 = reads from APB

1 = writes to APB.

PRDATA[31:0]

OUndefinedAPB read data.

PWDATA[31:0]

I-APB write data.
PREADYOb0APB slave ready. An APB slave can assert PREADY to extend a transfer.
PSLVERROb0

APB slave transfer error:

0 = no transfer error

1 = transfer error.

[1] This signal is not present when the processor is configured without the ETM.

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