full implementation of the ARM architecture v7-A instruction set

configurable 64-bit or 128-bit high-speed Advanced Microprocessor Bus Architecture (AMBA) with Advanced Extensible Interface (AXI) for main memory interface supporting multiple outstanding transactions

a pipeline for executing ARM integer instructions

a NEON pipeline for executing Advanced SIMD and VFP instruction sets

dynamic branch prediction with branch target address cache, global history buffer, and 8-entry return stack

Memory Management Unit (MMU) and separate instruction and data Translation Look-aside Buffers (TLBs) of 32 entries each

Level 1 instruction and data caches of 16KB or 32KB configurable size

Level 2 cache of 0KB, 128KB through 1MB configurable size

Level 2 cache with parity and Error Correction Code (ECC) configuration option

Embedded Trace Macrocell (ETM) support for non-invasive debug

static and dynamic power management including Intelligent Energy Management (IEM)

ARMv7 debug with watchpoint and breakpoint registers and a 32-bit Advanced Peripheral Bus (APB) slave interface to a CoreSight debug system.