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The bottom eight bits of a PSR are known collectively as the control bits. They are the:
The control bits change when an exception occurs. When the processor is operating in a privileged mode, software can manipulate these bits.
The I and F bits are the interrupt disable bits:
When the I bit is set to 1, IRQ interrupts are disabled.
When the F bit is set to 1, FIQ interrupts are disabled. FIQ can be nonmaskable in the Nonsecure state if the FW bit in SCR register is reset.
You can change the SPSR F bit in the Nonsecure state but this does not update the CPSR if the SCR bit [4] FW does not permit it.
The T bit reflects the operating state:
when the T bit is set to 1, the processor is executing in Thumb state or ThumbEE state depending on the J bit
when the T bit is cleared to 0, the processor is executing in ARM state.
Never use an MSR instruction to force a change
to the state of the T bit in the CPSR. If an MSR instruction
does try to modify this bit the result is architecturally Unpredictable. In
the processor, this bit is not affected.
M[4:0] are the mode bits. These bits determine the processor operating mode as Table 2.11 shows.
Table 2.11. PSR mode bit values
M[4:0] | Mode | Visible state registers | |
|---|---|---|---|
Thumb | ARM | ||
b10000 | User | r0–r7, r8-r12[1], SP, LR, PC, CPSR | r0–r14, PC, CPSR |
| b10001 | FIQ | r0–r7, r8_fiq-r12_fiqa, SP_fiq, LR_fiq PC, CPSR, SPSR_fiq | r0–r7, r8_fiq–r14_fiq, PC, CPSR, SPSR_fiq |
b10010 | IRQ | r0–r7, r8-r12a, SP_irq, LR_irq, PC, CPSR, SPSR_irq | r0–r12, r13_irq, r14_irq, PC, CPSR, SPSR_irq |
b10011 | Supervisor | r0–r7, r8-r12a, SP_svc, LR_svc, PC, CPSR, SPSR_svc | r0–r12, r13_svc, r14_svc, PC, CPSR, SPSR_svc |
b10111 | Abort | r0–r7, r8-r12a, SP_abt, LR_abt, PC, CPSR, SPSR_abt | r0–r12, r13_abt, r14_abt, PC, CPSR, SPSR_abt |
b11011 | Undefined | r0–r7, r8-r12a, SP_und, LR_und, PC, CPSR, SPSR_und | r0–r12, r13_und, r14_und, PC, CPSR, SPSR_und |
| b11111 | System | r0–r7, r8-r12a, SP, LR, PC, CPSR | r0–r14, PC, CPSR |
| b10110 | Secure Monitor | r0-r7, r8-r12a, SP_mon, LR_mon, PC, CPSR, SPSR_mon | r0-r12, PC, CPSR, SPSR_mon, r13_mon, r14_mon |
[1] In Thumb state, access to these registers is limited. | |||
| Copyright © 2006-2008 ARM Limited. All rights reserved. | ARM DDI 0344E |
| PDF version | |
| Home > Programmer’s Model > The program status registers > The control bits |