The Secure Configuration Register bits [3:1] determine which mode is entered when an IRQ, a FIQ, or an external abort exception occurs. The CP15 c12, Secure or Nonsecure Vector Base Address Register and the Monitor Vector Base Address Register define the base address of the Nonsecure, Secure, and Secure Monitor vector tables. If high vectors are enabled using CP15 c1 bit[13], the base address of the Nonsecure and Secure vector tables is 0xFFFF0000, regardless of the value of these registers. Enabling high vectors has no effect on the Secure Monitor vector addresses.