Cortex-A8 Technical Reference ManualRevision: r3p0
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Cortex™-A8 Technical Reference Manual

Revision: r3p0

Copyright © 2006-2008 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Additional reading
Feedback
Feedback on the product
Feedback on this manual
1. Introduction
1.1. About the processor
1.2. ARMv7-A architecture
1.3. Components of the processor
1.3.1. Instruction fetch
1.3.2. Instruction decode
1.3.3. Instruction execute
1.3.4. Load/store
1.3.5. L2 cache
1.3.6. NEON
1.3.7. ETM
1.4. External interfaces of the processor
1.4.1. AMBA AXI interface
1.4.2. AMBA APB interface
1.4.3. AMBA ATB interface
1.4.4. DFT interface
1.5. Debug
1.6. Power management
1.7. Configurable options
1.8. Product documentation and architecture
1.8.1. Documentation
1.8.2. Architectural information
1.9. Product revisions
2. Programmers Model
2.1. About the programmers model
2.2. Thumb-2 instruction set
2.3. ThumbEE instruction set
2.3.1. Instructions
2.3.2. Configuration
2.4. Jazelle Extension
2.4.1. Jazelle Identity Register
2.4.2. Jazelle Main Configuration Register
2.4.3. Jazelle OS Control Register
2.5. Security Extensions architecture
2.5.1. Security Extensions model
2.6. Advanced SIMD architecture
2.7. VFPv3 architecture
2.8. Processor operating states
2.8.1. Switching state
2.8.2. Interworking ARM and Thumb state
2.9. Data types
2.10. Memory formats
2.10.1. Byte-invariant big-endian format
2.10.2. Little-endian format
2.11. Addresses in a processor system
2.12. Operating modes
2.13. Registers
2.13.1. The state register set
2.14. The program status registers
2.14.1. The condition code flags
2.14.2. The Q flag
2.14.3. The IT execution state bits
2.14.4. The J bit
2.14.5. The GE[3:0] bits
2.14.6. The E bit
2.14.7. The A bit
2.14.8. The control bits
2.14.9. Modification of PSR bits by MSR instructions
2.14.10. Reserved bits
2.15. Exceptions
2.15.1. Exception entry and exit summary
2.15.2. Leaving an exception
2.15.3. Reset
2.15.4. Fast interrupt request
2.15.5. Interrupt request
2.15.6. Aborts
2.15.7. Imprecise data abort mask in the CPSR/SPSR
2.15.8. Software interrupt instruction
2.15.9. Software Monitor Instruction
2.15.10. Undefined instruction
2.15.11. Breakpoint instruction
2.15.12. Exception vectors
2.15.13. Exception priorities
2.16. Software consideration for Security Extensions
2.17. Hardware consideration for Security Extensions
2.17.1. System boot sequence
2.17.2. Security Extensions write access disable
2.17.3. Secure monitor bus
2.18. Control coprocessor
3. System Control Coprocessor
3.1. About the system control coprocessor
3.1.1. System control coprocessor functional groups
3.1.2. System control and configuration
3.1.3. MMU control and configuration
3.1.4. Cache control and configuration
3.1.5. L2 cache preload engine control and configuration
3.1.6. System performance monitor
3.1.7. Array debug
3.2. System control coprocessor registers
3.2.1. Register allocation
3.2.2. c0, Main ID Register
3.2.3. c0, Cache Type Register
3.2.4. c0, TCM Type Register
3.2.5. c0, TLB Type Register
3.2.6. c0, Multiprocessor ID Register
3.2.7. c0, Processor Feature Register 0
3.2.8. c0, Processor Feature Register 1
3.2.9. c0, Debug Feature Register 0
3.2.10. c0, Auxiliary Feature Register 0
3.2.11. c0, Memory Model Feature Register 0
3.2.12. c0, Memory Model Feature Register 1
3.2.13. c0, Memory Model Feature Register 2
3.2.14. c0, Memory Model Feature Register 3
3.2.15. c0, Instruction Set Attributes Register 0
3.2.16. c0, Instruction Set Attributes Register 1
3.2.17. c0, Instruction Set Attributes Register 2
3.2.18. c0, Instruction Set Attributes Register 3
3.2.19. c0, Instruction Set Attributes Register 4
3.2.20. c0, Instruction Set Attributes Registers 5-7
3.2.21. c0, Cache Level ID Register
3.2.22. c0, Silicon ID Register
3.2.23. c0, Cache Size Identification Registers
3.2.24. c0, Cache Size Selection Register
3.2.25. c1, Control Register
3.2.26. c1, Auxiliary Control Register
3.2.27. c1, Coprocessor Access Control Register
3.2.28. c1, Secure Configuration Register
3.2.29. c1, Secure Debug Enable Register
3.2.30. c1, Nonsecure Access Control Register
3.2.31. c2, Translation Table Base Register 0
3.2.32. c2, Translation Table Base Register 1
3.2.33. c2, Translation Table Base Control Register
3.2.34. c3, Domain Access Control Register
3.2.35. c5, Data Fault Status Register
3.2.36. c5, Instruction Fault Status Register
3.2.37. c5, Auxiliary Fault Status Registers
3.2.38. c6, Data Fault Address Register
3.2.39. c6, Instruction Fault Address Register
3.2.40. c7, Cache operations
3.2.41. c8, TLB operations
3.2.42. c9, Performance Monitor Control Register
3.2.43. c9, Count Enable Set Register
3.2.44. c9, Count Enable Clear Register
3.2.45. c9, Overflow Flag Status Register
3.2.46. c9, Software Increment Register
3.2.47. c9, Performance Counter Selection Register
3.2.48. c9, Cycle Count Register
3.2.49. c9, Event Selection Register
3.2.50. c9, Performance Monitor Count Registers
3.2.51. c9, User Enable Register
3.2.52. c9, Interrupt Enable Set Register
3.2.53. c9, Interrupt Enable Clear Register
3.2.54. c9, L2 Cache Lockdown Register
3.2.55. c9, L2 Cache Auxiliary Control Register
3.2.56. c10, TLB Lockdown Registers
3.2.57. c10, TLB preload operation
3.2.58. c10, Memory Region Remap Registers
3.2.59. c11, PLE Identification and Status Registers
3.2.60. c11, PLE User Accessibility Register
3.2.61. c11, PLE Channel Number Register
3.2.62. c11, PLE enable commands
3.2.63. c11, PLE Control Register
3.2.64. c11, PLE Internal Start Address Register
3.2.65. c11, PLE Internal End Address Register
3.2.66. c11, PLE Channel Status Register
3.2.67. c11, PLE Context ID Register
3.2.68. c12, Secure or Nonsecure Vector Base Address Register
3.2.69. c12, Monitor Vector Base Address Register
3.2.70. c12, Interrupt Status Register
3.2.71. c13, FCSE PID Register
3.2.72. c13, Context ID Register
3.2.73. c13, Thread and Process ID Registers
3.2.74. c15, L1 system array debug data registers
3.2.75. c15, L1 TLB operations
3.2.76. c15, L1 HVAB array operations
3.2.77. c15, L1 tag array operations
3.2.78. c15, L1 data array operations
3.2.79. c15, BTB array operations
3.2.80. c15, GHB array operations
3.2.81. c15, L2 system array debug data registers
3.2.82. c15, L2 parity/ECC array operations
3.2.83. c15, L2 tag array operations
3.2.84. c15, L2 data array operations
4. Unaligned Data and Mixed-endian Data Support
4.1. About unaligned and mixed-endian data
4.2. Unaligned data access support
4.2.1. NEON data alignment
4.3. Mixed-endian access support
5. Program Flow Prediction
5.1. About program flow prediction
5.2. Predicted instructions
5.2.1. Return stack predictions
5.3. Nonpredicted instructions
5.4. Guidelines for optimal performance
5.5. Enabling program flow prediction
5.6. Operating system and predictor context
5.6.1. Instruction memory barriers
6. Memory Management Unit
6.1. About the MMU
6.2. Memory access sequence
6.2.1. TLB match process
6.3. 16MB supersection support
6.4. MMU interaction with memory system
6.5. External aborts
6.5.1. External aborts on data read or write
6.5.2. Precise and imprecise aborts
6.6. TLB lockdown
6.7. MMU software-accessible registers
7. Level 1 Memory System
7.1. About the L1 memory system
7.2. Cache organization
7.2.1. Cache control operations
7.2.2. Cache miss handling
7.2.3. Cache disabled behavior
7.2.4. Unexpected hit behavior
7.2.5. Cache parity error detection
7.2.6. Instruction cache maintenance
7.3. Memory attributes
7.3.1. Strongly ordered
7.3.2. Device
7.3.3. Normal
7.4. Cache debug
7.5. Data cache features
7.5.1. Data cache preload instruction
7.5.2. Data cache behavior with C-bit disabled
7.6. Instruction cache features
7.6.1. Instruction cache preload instruction
7.6.2. Instruction cache speculative memory accesses
7.6.3. Instruction cache disabled behavior
7.7. Hardware support for virtual aliasing conditions
7.8. Parity detection
8. Level 2 Memory System
8.1. About the L2 memory system
8.2. Cache organization
8.2.1. L2 cache bank structure
8.2.2. L2 cache transfer policy
8.3. Enabling and disabling the L2 cache controller
8.4. L2 PLE
8.4.1. Configuring the preload engine
8.4.2. Preload engine commands and status interaction
8.4.3. Interaction of the preload engine with WFI
8.4.4. Memory region interaction with the preload engine
8.4.5. Processor configuration and the impact on the preload engine
8.4.6. Effects of cache maintenance operations during preloading engine transfers
8.5. Synchronization primitives
8.5.1. Load-exclusive instruction
8.5.2. Store-exclusive instruction
8.5.3. Example of LDREX and STREX usage
8.6. Locked access
8.7. Parity and error correction code
9. External Memory Interface
9.1. About the external memory interface
9.1.1. External interface servicing instruction fetch transactions
9.1.2. External interface servicing data transactions
9.2. AXI control signals in the processor
9.2.1. AXI identifiers
9.2.2. Read/write data bus width configuration pin
9.3. AXI instruction transactions
9.3.1. AXI instruction address transactions
9.4. AXI data read/write transactions
9.4.1. Linefills
9.4.2. Evictions
9.4.3. NEON accesses to strongly ordered and device memory
9.4.4. AXI data address transactions
10. Clock, Reset, and Power Control
10.1. Clock domains
10.1.1. AXI clocking using ACLKEN
10.1.2. Debug clocking using PCLKEN
10.1.3. ATB clocking using ATCLKEN
10.2. Reset domains
10.2.1. Power-on reset
10.2.2. Soft reset
10.2.3. APB and ATB reset
10.2.4. Hardware RAM array reset
10.2.5. Reset of memory arrays
10.3. Power control
10.3.1. Dynamic power management
10.3.2. Static or leakage power management
10.3.3. Debugging the processor while powered down
10.3.4. L1 data and L2 cache power domains
10.3.5. Special note on reset during power transition
11. Design for Test
11.1. MBIST
11.1.1. About MBIST
11.1.2. MBIST registers
11.1.3. MBIST operation
11.1.4. Pattern selection
11.2. ATPG test features
11.2.1. Wrapper
11.2.2. Enabling sections of the core
11.2.3. Reset handling
11.2.4. Safe shift RAM signals
12. Debug
12.1. Debug systems
12.1.1. Debug host
12.1.2. Protocol converter
12.1.3. Debug target
12.2. About the debug unit
12.2.1. Halting debug-mode debugging
12.2.2. Monitor debug-mode debugging
12.2.3. Security extensions and debug
12.2.4. Programming the debug unit
12.3. Debug register interface
12.3.1. Coprocessor registers
12.3.2. CP14 access permissions
12.3.3. Coprocessor registers summary
12.3.4. Memory-mapped registers
12.3.5. Memory addresses for breakpoints and watchpoints
12.3.6. Power domains and debug
12.3.7. Effects of resets on debug registers
12.3.8. APB interface access permissions
12.4. Debug register descriptions
12.4.1. Accessing debug registers
12.4.2. CP14 c0, Debug ID Register
12.4.3. CP14 c0, Debug ROM Address Register
12.4.4. CP14 c0, Debug Self Address Offset Register
12.4.5. CP14 c1, Debug Status and Control Register
12.4.6. Data Transfer Register
12.4.7. Watchpoint Fault Address Register
12.4.8. Vector Catch Register
12.4.9. Event Catch Register
12.4.10. Debug State Cache Control Register
12.4.11. Instruction Transfer Register
12.4.12. Debug Run Control Register
12.4.13. Breakpoint Value Registers
12.4.14. Breakpoint Control Registers
12.4.15. Watchpoint Value Registers
12.4.16. Watchpoint Control Registers
12.4.17. Operating System Lock Access Register
12.4.18. Operating System Lock Status Register
12.4.19. Operating System Save and Restore Register
12.4.20. Device Power Down and Reset Control Register
12.4.21. Device Power Down and Reset Status Register
12.5. Management registers
12.5.1. Processor ID Registers
12.5.2. Integration Internal Output Control Register
12.5.3. Integration External Output Control Register
12.5.4. Integration Input Status Register
12.5.5. Integration Mode Control Register
12.5.6. Claim Tag Set Register
12.5.7. Claim Tag Clear Register
12.5.8. Lock Access Register
12.5.9. Lock Status Register
12.5.10. Authentication Status Register
12.5.11. Device Type Register
12.5.12. Identification Registers
12.6. Debug events
12.6.1. Software debug event
12.6.2. Halting debug event
12.6.3. Behavior of the processor on debug events
12.6.4. Debug event priority
12.6.5. Watchpoint debug events
12.7. Debug exception
12.7.1. Effect of debug exceptions on CP15 registers and WFAR
12.7.2. Avoiding unrecoverable states
12.8. Debug state
12.8.1. Entering debug state
12.8.2. Behavior of the PC and CPSR in debug state
12.8.3. Executing instructions in debug state
12.8.4. Writing to the CPSR in debug state
12.8.5. Privilege
12.8.6. Effect of debug state on noninvasive debug
12.8.7. Effects of debug events on registers
12.8.8. Exceptions in debug state
12.8.9. Leaving debug state
12.9. Cache debug
12.9.1. Cache pollution in debug state
12.9.2. Cache coherency in debug state
12.9.3. Cache usage profiling
12.10. External debug interface
12.10.1. Miscellaneous debug signals
12.10.2. Authentication signals
12.11. Using the debug functionality
12.11.1. Debug communications channel
12.11.2. Programming breakpoints and watchpoints
12.11.3. Single-stepping
12.11.4. Debug state entry
12.11.5. Debug state exit
12.11.6. Accessing registers and memory in debug state
12.12. Debugging systems with energy management capabilities
12.12.1. Standby
12.12.2. Emulating power down
12.12.3. Detecting power down
12.12.4. Operating system support
12.12.5. Registers available during power down
12.12.6. Scenarios and usage models
13. NEON and VFP Programmers Model
13.1. About the NEON and VFP programmers model
13.1.1. NEON media coprocessor
13.1.2. VFP coprocessor
13.2. General-purpose registers
13.2.1. NEON views of the register bank
13.2.2. VFP views of the register bank
13.3. Short vectors
13.3.1. About register banks
13.3.2. Operations using register banks
13.4. System registers
13.4.1. Floating-Point System ID Register, FPSID
13.4.2. Floating-Point Status and Control Register, FPSCR
13.4.3. Floating-point exception Register, FPEXC
13.4.4. Media and VFP Feature Registers, MVFR0 and MVFR1
13.5. Modes of operation
13.5.1. Full-compliance mode
13.5.2. Flush-to-zero mode
13.5.3. Default NaN mode
13.5.4. RunFast mode
13.6. Compliance with the IEEE 754 standard
13.6.1. Complete implementation of the IEEE 754 standard
13.6.2. IEEE 754 standard implementation choices
14. Embedded Trace Macrocell
14.1. About the ETM
14.1.1. ETM features
14.1.2. The debug environment
14.1.3. NEON
14.2. ETM configuration
14.3. ETM register summary
14.4. ETM register descriptions
14.4.1. ID Register
14.4.2. Configuration Code Register
14.4.3. Configuration Code Extension Register
14.4.4. Peripheral Identification Registers
14.4.5. Component Identification Registers
14.4.6. Integration Test Registers
14.5. Precision of TraceEnable and ViewData
14.5.1. TraceEnable
14.5.2. ViewData
14.5.3. Enabling events
14.5.4. Address comparators
14.6. Exact match bit
14.6.1. Address comparators configured for instruction addresses
14.6.2. Address comparators configured for data addresses
14.6.3. Address range comparators
14.7. Context ID tracing
14.8. Instrumentation instructions
14.9. Idle state control
14.10. Interaction with the Performance Monitoring Unit
14.10.1. Use of PMU events by the ETM
14.10.2. Use of ETM events by the PMU
15. Cross Trigger Interface
15.1. About the CTI
15.1.1. How the CTI works
15.1.2. The channel interface
15.1.3. Trigger signal synchronization
15.2. Trigger inputs and outputs
15.3. Connecting asynchronous channel interfaces
15.4. About the CTI programmers model
15.5. CTI register summary
15.6. CTI register descriptions
15.6.1. CTI Control Register, CTICONTROL
15.6.2. CTI Interrupt Acknowledge Register, CTIINTACK
15.6.3. CTI Application Trigger Set Register, CTIAPPSET
15.6.4. CTI Application Trigger Clear Register, CTIAPPCLEAR
15.6.5. CTI Application Pulse Register, CTIAPPPULSE
15.6.6. CTI Trigger to Channel Enable Registers, CTIINEN0-8
15.6.7. CTI Channel to Trigger Enable Registers, CTIOUTEN0-8
15.6.8. CTI Trigger In Status Register, CTITRIGINSTATUS
15.6.9. CTI Trigger Out Status Register, CTITRIGOUTSTATUS
15.6.10. CTI Channel In Status Register, CTICHINSTATUS
15.6.11. CTI Channel Gate Register, CTICHGATE
15.6.12. ASIC Control Register, ASICCTL
15.6.13. CTI Channel Out Status Register, CTICHOUTSTATUS
15.7. CTI Integration Test Registers
15.7.1. ITTRIGINACK, 0xEE0
15.7.2. ITCHOUT, 0xEE4
15.7.3. ITTRIGOUT, 0xEE8
15.7.4. ITTRIGOUTACK, 0xEF0
15.7.5. ITCHIN, 0xEF4
15.7.6. ITTRIGIN, 0xEF8
15.8. CTI CoreSight defined registers
15.8.1. Authentication Status Register, 0xFB8
15.8.2. Device ID Register, 0xFC8
15.8.3. Device Type Identifier, 0xFCC
15.8.4. Peripheral Identification Registers
15.8.5. Component Identification Registers
16. Instruction Cycle Timing
16.1. About instruction cycle timing
16.2. Instruction-specific scheduling for ARM instructions
16.2.1. Example of how to read ARM instruction tables
16.2.2. Data-processing instructions
16.2.3. Multiply instructions
16.2.4. Parallel arithmetic and DSP instructions
16.2.5. Extended instructions
16.2.6. Miscellaneous data-processing instructions
16.2.7. Status register access instructions
16.2.8. Load/store instructions
16.2.9. Load multiple and store multiple instructions
16.2.10. Branch instructions
16.2.11. Coprocessor instructions
16.3. Dual-instruction issue restrictions
16.4. Other pipeline-dependent latencies
16.4.1. Cycle penalty for instruction flow change
16.4.2. Memory system effects on instruction timings
16.4.3. Thumb-2 instructions
16.4.4. ThumbEE instructions
16.4.5. Conditional instructions
16.5. Advanced SIMD instruction scheduling
16.5.1. Mixed ARM and Advanced SIMD instruction sequences
16.5.2. Passing data between ARM and NEON
16.5.3. Dual issue for Advanced SIMD instructions
16.6. Instruction-specific scheduling for Advanced SIMD instructions
16.6.1. Example of how to read Advanced SIMD instruction tables
16.6.2. Advanced SIMD integer ALU instructions
16.6.3. Advanced SIMD integer multiply instructions
16.6.4. Advanced SIMD integer shift instructions
16.6.5. Advanced SIMD floating-point instructions
16.6.6. Advanced SIMD byte permute instructions
16.6.7. Advanced SIMD load/store instructions
16.6.8. Advanced SIMD register transfer instructions
16.7. VFP instructions
16.7.1. VFP instruction execution in the VFP coprocessor
16.7.2. VFP instruction execution in the NFP pipeline
16.8. Scheduling example
17. AC Characteristics
17.1. About setup and hold times
17.2. AXI interface
17.3. ATB and CTI interfaces
17.4. APB interface and miscellaneous debug signals
17.5. L1 and L2 MBIST interfaces
17.6. L2 preload interface
17.7. DFT interface
17.8. Miscellaneous signals
A. Signal Descriptions
A.1. AXI interface
A.2. ATB interface
A.3. MBIST and DFT interface
A.3.1. MBIST interface
A.3.2. DFT pins and additional MBIST pin requirements during MBIST testing
A.4. Preload engine interface
A.5. APB interface
A.6. Miscellaneous signals
A.7. Miscellaneous debug signals
A.8. Miscellaneous ETM and CTI signals
B. Instruction Mnemonics
B.1. Advanced SIMD data-processing instructions
B.2. VFP data-processing instructions
C. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Cortex-A8 block diagram
2.1. 32-bit ARM Thumb-2 instruction format
2.2. ThumbEE Configuration Register format
2.3. ThumbEE HandlerBase Register format
2.4. Jazelle Identity Register format
2.5. Jazelle Main Configuration Register format
2.6. Jazelle OS Control Register format
2.7. Secure and Nonsecure states
2.8. Big-endian addresses of bytes within words
2.9. Little-endian addresses of bytes within words
2.10. Register organization in ARM state
2.11. Processor register set showing banked registers
2.12. Program status register
3.1. Main ID Register format
3.2. Cache Type Register format
3.3. TLB Type Register format
3.4. Processor Feature Register 0 format
3.5. Processor Feature Register 1 format
3.6. Debug Feature Register 0 format
3.7. Memory Model Feature Register 0 format
3.8. Memory Model Feature Register 1 format
3.9. Memory Model Feature Register 2 format
3.10. Memory Model Feature Register 3 format
3.11. Instruction Set Attributes Register 0 format
3.12. Instruction Set Attributes Register 1 format
3.13. Instruction Set Attributes Register 2 format
3.14. Instruction Set Attributes Register 3 format
3.15. Instruction Set Attributes Register 4 format
3.16. Cache Level ID Register format
3.17. Silicon ID Register format
3.18. Cache Size Identification Register format
3.19. Cache Size Selection Register format
3.20. Control Register bit assignments
3.21. Auxiliary Control Register format
3.22. Coprocessor Access Control Register format
3.23. Secure Configuration Register format
3.24. Secure Debug Enable Register format
3.25. Nonsecure Access Control Register format
3.26. Translation Table Base Register 0 format
3.27. Translation Table Base Register 1 format
3.28. Translation Table Base Control Register format
3.29. Domain Access Control Register format
3.30. Data Fault Status Register format
3.31. Instruction Fault Status Register format
3.32. c7 format for set and way
3.33. c7 format for MVA
3.34. PA Register format for successful translation
3.35. PA Register format for unsuccessful translation
3.36. TLB Operations MVA and ASID format
3.37. TLB Operations ASID format
3.38. Performance Monitor Control Register format
3.39. Count Enable Set Register format
3.40. Count Enable Clear Register format
3.41. Overflow Flag Status Register format
3.42. Software Increment Register format
3.43. Performance Counter Selection Register format
3.44. Event Selection Register format
3.45. User Enable Register format
3.46. Interrupt Enable Set Register format
3.47. Interrupt Enable Clear Register format
3.48. L2 Cache Lockdown Register format
3.49. L2 Cache Auxiliary Control Register format
3.50. TLB Lockdown Register format
3.51. Primary Region Remap Register format
3.52. Normal Memory Remap Register format
3.53. PLE identification and Status Registers format
3.54. PLE User Accessibility Register format
3.55. PLE Channel Number Register format
3.56. PLE Control Register format
3.57. PLE Internal Start Address Register bit format
3.58. PLE Internal End Address Register format
3.59. PLE Channel Status Register format
3.60. PLE Context ID Register format
3.61. Secure or Nonsecure Vector Base Address Register format
3.62. Monitor Vector Base Address Register format
3.63. Interrupt Status Register format
3.64. FCSE PID Register format
3.65. Address mapping with the FCSE PID Register
3.66. Context ID Register format
3.67. Instruction and Data side Data 0 Registers format
3.68. Instruction and Data side Data 1 Registers format
3.69. L1 TLB CAM read operation format
3.70. L1 TLB CAM write operation format
3.71. L1 HVAB array read operation format
3.72. L1 HVAB array write operation format
3.73. L1 tag array read operation format
3.74. L1 tag array write operation format
3.75. L1 data array read operation format
3.76. L1 data array write operation format
3.77. BTB array read operation format
3.78. BTB array write operation format
3.79. GHB array read operation format
3.80. GHB array write operation format
3.81. L2 Data 0 Register format
3.82. L2 Data 1 Register format
3.83. L2 Data 2 Register format
3.84. L2 parity/ECC array read operation format
3.85. L2 parity/ECC array write operation format
3.86. L2 tag array read operation format
3.87. L2 tag array write operation format
3.88. L2 data RAM array read operation format
3.89. L2 data RAM array write operation format
6.1. 16MB supersection descriptor format
8.1. L2 cache bank structure
10.1. CLK duty cycle
10.2. CLK-to-ACLK ratio of 4:1
10.3. Changing the CLK-to-ACLK ratio from 4:1 to 1:1
10.4. Changing the PCLK-to-internal-PCLK ratio from 4:1 to 1:1
10.5. Changing the ATCLK-to-internal-ATCLK ratio from 4:1 to 1:1
10.6. Power-on reset timing
10.7. Soft reset timing
10.8. PRESETn and ATRESETn assertion
10.9. STANDBYWFI deassertion
10.10. CLKSTOPREQ and CLKSTOPACK
10.11. Power domains
10.12. Voltage domains
10.13. Retention power domains
11.1. L1 MBIST Instruction Register bit assignments
11.2. L2 MBIST Instruction Register bit assignments
11.3. L1 and L2 MBIST GO-NOGO Instruction Registers bit assignments
11.4. L1 MBIST GO-NOGO Instruction Register example with two patterns
11.5. L1 MBIST Datalog Register bit assignments
11.6. L2 MBIST Datalog Register bit assignments
11.7. Timing of MBIST instruction load
11.8. Timing of MBIST custom GO-NOGO instruction load
11.9. Timing of MBIST at-speed execution
11.10. Timing of MBIST end-of-test datalog retrieval
11.11. Timing of MBIST start of bitmap datalog retrieval
11.12. Timing of MBIST end of bitmap datalog retrieval
11.13. Physical array after pass 1 of CKBD
11.14. Physical array after pass 1 of COLBAR
11.15. Physical array after pass 1 of ROWBAR
11.16. Row 1 column 2 state during pass 2 of RWXMARCH
11.17. Row 1 column 2 state during pass 2 of RWYMARCH
11.18. Row 1 column 2 state during pass 2 of RWRXMARCH
11.19. Row 1 column 2 state during pass 2 of RWRYMARCH
11.20. Row 1 column 2 state during pass 2 of XMARCHC
11.21. Row 1 column 2 state during pass 2 of YMARCHC
11.22. XADDRBAR array accessing and data
11.23. YADDRBAR array accessing and data
11.24. WRITEBANG
11.25. READBANG
11.26. Input wrapper boundary register cell control logic
11.27. Output wrapper boundary register cell control logic
11.28. IEEE 1500-compliant input wrapper boundary register cell
11.29. Reset handling
11.30. Safe shift RAM signal
12.1. Typical debug system
12.2. Debug ID Register format
12.3. Debug ROM Address Register format
12.4. Debug Self Address Offset Register format
12.5. Debug Status and Control Register format
12.6. DTR Register format
12.7. Vector Catch Register format
12.8. Event Catch Register format
12.9. Debug State Cache Control Register format
12.10. ITR format
12.11. Debug Run Control Register format
12.12. Breakpoint Control Registers format
12.13. Watchpoint Control Registers format
12.14. OS Lock Access Register format
12.15. OS Lock Status Register format
12.16. OS Save and Restore Register format
12.17. PRCR format
12.18. PRSR format
12.19. Integration Internal Output Control Register format
12.20. Integration External Output Control Register format
12.21. Integration Input Status Register format
12.22. Integration Mode Control Register format
12.23. Claim Tag Set Register format
12.24. Claim Tag Clear Register format
12.25. Lock Access Register format
12.26. Lock Status Register format
12.27. Authentication Status Register format
12.28. Device Type Register format
12.29. Timing of core power-down and power-up sequences
13.1. NEON and VFP register bank
13.2. Register banks
13.3. Floating-Point System ID Register format
13.4. Floating-Point Status and Control Register format
13.5. Floating-Point Exception Register format
13.6. MVFR0 Register format
13.7. MVFR1 Register format
14.1. Example CoreSight debug environment
14.2. ID Register format
14.3. Configuration Code Register format
14.4. Configuration Code Extension Register format
14.5. Mapping between the Component ID Registers and the component ID value
14.6. ITMISCOUT Register format
14.7. ITMISCIN Register format
14.8. ITTRIGGER Register format
14.9. ITATBDATA0 Register format
14.10. ITATBCTR2 Register format
14.11. ITATBCTR1 Register format
14.12. ITATBCTR0 Register format
15.1. Debug system components
15.2. Cross Trigger Interface channels
15.3. Asynchronous to synchronous converter
15.4. CTI Control Register format
15.5. CTI Interrupt Acknowledge Register format
15.6. CTI Application Trigger Set Register format
15.7. CTI Application Trigger Clear Register format
15.8. CTI Application Pulse Register format
15.9. CTI Trigger to Channel Enable Registers format
15.10. CTI Channel to Trigger Enable Registers format
15.11. CTI Trigger In Status Register format
15.12. CTI Trigger Out Status Register format
15.13. CTI Channel In Status Register format
15.14. CTI Channel Gate Register format
15.15. ASIC Control Register format
15.16. CTI Channel Out Status Register format
15.17. ITTRIGINACK Register format
15.18. ITCHOUT Register format
15.19. ITTRIGOUT Register format
15.20. ITTRIGOUTACK Register format
15.21. ITCHIN Register format
15.22. ITTRIGIN Register format
15.23. Mapping between the Component ID Registers and the component ID value
17.1. Input timing parameters
17.2. Output timing parameters

List of Tables

1.1. Cortex-A8 configurable options
2.1. ThumbEE Configuration Register bit functions
2.2. ThumbEE HandlerBase Register bit functions
2.3. Access to ThumbEE registers
2.4. Jazelle Identity Register bit functions
2.5. Jazelle Main Configuration Register bit functions
2.6. Jazelle OS Control Register bit functions
2.7. Address types in the processor system
2.8. Mode structure
2.9. Register mode identifiers
2.10. GE[3:0] settings
2.11. PSR mode bit values
2.12. Exception entry and exit
2.13. Exception priorities
3.1. System control coprocessor register functions
3.2. CP15 registers affected by CP15SDISABLE
3.3. Summary of CP15 registers and operations
3.4. Main ID Register bit functions
3.5. Results of access to the Main ID Register
3.6. Cache Type Register bit functions
3.7. Results of access to the Cache Type Register
3.8. Results of access to the TCM Type Register
3.9. TLB Type Register bit functions
3.10. Results of access to the TLB Type Register
3.11. Results of access to the Multiprocessor ID Register
3.12. Processor Feature Register 0 bit functions
3.13. Results of access to the Processor Feature Register 0
3.14. Processor Feature Register 1 bit functions
3.15. Results of access to Processor Feature Register 1
3.16. Debug Feature Register 0 bit functions
3.17. Results of access to Debug Feature Register 0
3.18. Results of access to Auxiliary Feature Register 0
3.19. Memory Model Feature Register 0 bit functions
3.20. Results of access to Memory Model Feature Register 0
3.21. Memory Model Feature Register 1 bit functions
3.22. Results of access to Memory Model Feature Register 1
3.23. Memory Model Feature Register 2 bit functions
3.24. Results of access to Memory Model Feature Register 2
3.25. Memory Model Feature Register 3 bit functions
3.26. Results of access to Memory Model Feature Register 3
3.27. Instruction Set Attributes Register 0 bit functions
3.28. Results of access to Instruction Set Attributes Register 0
3.29. Instruction Set Attributes Register 1 bit functions
3.30. Results of access to Instruction Set Attributes Register 1
3.31. Instruction Set Attributes Register 2 bit functions
3.32. Results of access to Instruction Set Attributes Register 2
3.33. Instruction Set Attributes Register 3 bit functions
3.34. Results of access to Instruction Set Attributes Register 3
3.35. Instruction Set Attributes Register 4 bit functions
3.36. Results of access to Instruction Set Attributes Register 4
3.37. Cache Level ID Register bit functions
3.38. Results of access to the Cache Level ID Register
3.39. Silicon ID Register bit functions
3.40. Results of access to the Silicon ID Register
3.41. Cache Size Identification Register bit functions
3.42. Encodings of the Cache Size Identification Register
3.43. Results of access to the Cache Size Identification Register
3.44. Cache Size Selection Register bit functions
3.45. Results of access to the Cache Size Selection Register
3.46. Control Register bit functions
3.47. Results of access to the Control Register
3.48. Behavior of the processor when enabling caches
3.49. Auxiliary Control Register bit functions
3.50. Results of access to the Auxiliary Control Register
3.51. Coprocessor Access Control Register bit functions
3.52. Results of access to the Coprocessor Access Control Register
3.53. Secure Configuration Register bit functions
3.54. Operation of the FW and FIQ bits
3.55. Operation of the AW and EA bits
3.56. Secure Debug Enable Register bit functions
3.57. Results of access to the Secure Debug Enable Register
3.58. Nonsecure Access Control Register bit functions
3.59. Results of access to the Auxiliary Control Register
3.60. Translation Table Base Register 0 bit functions
3.61. Results of access to the Translation Table Base Register 0
3.62. Translation Table Base Register 1 bit functions
3.63. Results of access to the Translation Table Base Register 1
3.64. Translation Table Base Control Register bit functions
3.65. Results of access to the Translation Table Base Control Register
3.66. Domain Access Control Register bit functions
3.67. Results of access to the Domain Access Control Register
3.68. Data Fault Status Register bit functions
3.69. Instruction Fault Status Register bit functions
3.70. Results of access to the Auxiliary Fault Status Registers
3.71. Results of access to the Data Fault Address Register
3.72. Results of access to the Instruction Fault Address Register
3.73. Register c7 cache and prefetch buffer maintenance operations
3.74. Functional bits of c7 for set and way
3.75. Values of A, L, and S for L1 cache sizes
3.76. Values of A, L, and S for L2 cache sizes
3.77. Functional bits of c7 for MVA
3.78. PA Register for successful translation bit functions
3.79. PA Register for unsuccessful translation bit functions
3.80. Results of access to the data synchronization barrier operation
3.81. Results of access to the data memory barrier operation
3.82. Performance Monitor Control Register bit functions
3.83. Results of access to the Performance Monitor Control Register
3.84. Count Enable Set Register bit functions
3.85. Results of access to the Count Enable Set Register
3.86. Count Enable Clear Register bit functions
3.87. Results of access to the Count Enable Clear Register
3.88. Overflow Flag Status Register bit functions
3.89. Results of access to the Overflow Flag Status Register
3.90. Software Increment Register bit functions
3.91. Results of access to the Software Increment Register
3.92. Performance Counter Selection Register bit functions
3.93. Results of access to the Performance Counter Selection Register
3.94. Results of access to the Cycle Count Register
3.95. Event Selection Register bit functions
3.96. Results of access to the Event Selection Register
3.97. Values for predefined events
3.98. Results of access to the Performance Monitor Count Registers
3.99. Signal settings for the Performance Monitor Count Registers
3.100. User Enable Register bit functions
3.101. Results of access to the User Enable Register
3.102. Interrupt Enable Set Register bit functions
3.103. Results of access to the Interrupt Enable Set Register
3.104. Interrupt Enable Clear Register bit functions
3.105. Results of access to the Interrupt Enable Clear Register
3.106. L2 Cache Lockdown Register bit functions
3.107. Results of access to the L2 Cache Lockdown Register
3.108. L2 Cache Auxiliary Control Register bit functions
3.109. Results of access to the L2 Cache Auxiliary Control Register
3.110. TLB Lockdown Register bit functions
3.111. Results of access to the TLB Lockdown Register
3.112. Application of remapped registers on memory access
3.113. Primary Region Remap Register bit functions
3.114. Encoding for the remapping of the primary memory type
3.115. Normal Memory Remap Register bit functions
3.116. Remap encoding for inner or outer cacheable attributes
3.117. Results of access to the memory region remap registers
3.118. PLE Identification and Status Register bit functions
3.119. Opcode_2 values for PLE Identification and Status Register functions
3.120. Results of access to the PLE Identification and Status Registers
3.121. PLE User Accessibility Register bit functions
3.122. Results of access to the PLE User Accessibility Register
3.123. PLE Channel Number Register bit functions
3.124. Results of access to the PLE User Accessibility Register
3.125. Results of access to the PLE enable commands
3.126. PLE Control Register bit functions
3.127. Writing to UM bit [26]
3.128. Results of access to the PLE Control Registers
3.129. Results of access to the PLE Internal Start Address Register
3.130. Maximum transfer size for various L2 cache sizes
3.131. Results of access to the PLE Internal End Address Register
3.132. PLE Channel Status Register bit functions
3.133. Results of access to the PLE Channel Status Register
3.134. PLE Context ID Register bit functions
3.135. Results of access to the PLE Context ID Register
3.136. Secure or Nonsecure Vector Base Address Register bit functions
3.137. Results of access to the Secure or Nonsecure Vector Base Address Register
3.138. Monitor Vector Base Address Register bit functions
3.139. Results of access to the Monitor Vector Base Address Register
3.140. Interrupt Status Register bit functions
3.141. Results of access to the Interrupt Status Register
3.142. FCSE PID Register bit functions
3.143. Results of access to the FCSE PID Register
3.144. Context ID Register bit functions
3.145. Results of access to the Context ID Register
3.146. Results of access to the Thread and Process ID Registers
3.147. Functional bits of I-L1 or D-L1 Data 0 Register for a TLB CAM operation
3.148. Functional bits of I-L1 or D-L1 Data 1 Register for a TLB CAM operation
3.149. Functional bits of I-L1 or D-L1 Data 0 Register for a TLB ATTR operation
3.150. Functional bits of I-L1 or D-L1 Data 0 Register for a TLB PA array operation
3.151. Functional bits of I-L1 or D-L1 Data 0 Register for an HVAB array operation
3.152. Functional bits of I-L1 or D-L1 Data 0 Register for an L1 tag array operation
3.153. Functional bits of I-L1 or D-L1 Data 0 Register for L1 data array operation
3.154. Functional bits of I-L1 or D-L1 Data 1 Register for L1 data array operation
3.155. Functional bits of I-L1 Data 0 Register for a BTB array operation
3.156. Functional bits of I-L1 Data 1 Register for a BTB array operation
3.157. Functional bits of I-L1 Data 0 Register for a GHB array operation
3.158. Functional bits of L2 Data 0 Register for an L2 parity/ECC operation
3.159. Functional bits of L2 Data 0 Register for a tag RAM operation
3.160. Functional bits of L2 Data 0 Register for a data RAM operation
3.161. Functional bits of L2 Data 1 Register for a data RAM operation
3.162. Functional bits of L2 Data 2 Register for a data RAM operation
3.163. Address field values
4.1. NEON normal memory alignment qualifiers
6.1. CP15 register functions
7.1. Memory types affecting L1 and L2 cache flows
8.1. L2 cache transfer policy
8.2. Cacheable and noncacheable memory region types
9.1. Read address channel AXI ID
9.2. Write address channel AXI ID
9.3. AXI master interface attributes
9.4. A64n128 encoding
9.5. AXI address channel for instruction transactions
9.6. Number of transfers on AXI write channel for an eviction
9.7. AXI address channel for data transactions - excluding load/store multiples
9.8. AXI address channel for data transactions for load/store multiples
10.1. Reset inputs
10.2. Valid power domains
11.1. MBIST register summary
11.2. Selecting a test pattern with pttn[5:0]
11.3. Selecting the L1 arrays to test with L1_array_sel[22:0]
11.4. L1_config[14:0]
11.5. Configuring the number of L1 array rows with L1_config[14:0]
11.6. Selecting L2 RAMs for test with L2_ram_sel[4:0]
11.7. L2_config[22:0]
11.8. Selecting L2 data array latency with L2DLat[3:0]
11.9. Selecting L2 tag array latency with L2TLat[1:0]
11.10. Selecting the L2 RAMs with L2Rows[11:0]
11.11. Configuring the number of L2 RAM rows with L2Rows[11:0]
11.12. Valid L2 array row numbers
11.13. Selecting the L2ValSer test type
11.14. Selecting L2 RAMs for LSB control
11.15. Selecting counting sequence of L2 RAM column address LSBs
11.16. GNG[10:0] field
11.17. L2 cache way grouping
11.18. Identifying failing L2 bits with failing_bits[32:0]
11.19. Summary of MBIST patterns
12.1. Access to CP14 debug registers
12.2. CP14 debug registers summary
12.3. Debug memory-mapped registers
12.4. Processor reset effect on debug and ETM logic
12.5. APB interface access with relation to software lock
12.6. Debug registers access with relation to power-down event
12.7. Power management registers access with relation to power-down event
12.8. ETM and CTI registers access with relation to power-down event
12.9. Terms used in register descriptions
12.10. CP14 debug registers
12.11. Debug ID Register bit functions
12.12. Debug ROM Address Register bit functions
12.13. Debug Self Address Offset Register bit functions
12.14. Debug Status and Control Register bit functions
12.15. Data Transfer Register bit functions
12.16. Watchpoint Fault Address Register bit functions
12.17. Vector Catch Register bit functions
12.18. Event Catch Register bit functions
12.19. Debug State Cache Control Register bit functions
12.20. Instruction Transfer Register bit functions
12.21. Debug Run Control Register bit functions
12.22. Breakpoint Value Registers bit functions
12.23. Breakpoint Control Registers bit functions
12.24. Meaning of BVR bits [22:20]
12.25. Watchpoint Value Registers bit functions
12.26. Watchpoint Control Registers bit functions
12.27. OS Lock Access Register bit functions
12.28. OS Lock Status Register bit functions
12.29. OS Save and Restore Register bit functions
12.30. PRCR bit functions
12.31. PRSR bit functions
12.32. Management registers
12.33. Processor Identifier Registers
12.34. Integration Internal Output Control Register bit functions
12.35. Integration External Output Control Register bit functions
12.36. Integration Input Status Register bit functions
12.37. Integration Mode Control Register bit functions
12.38. Claim Tag Set Register bit functions
12.39. Claim Tag Clear Register bit functions
12.40. Lock Access Register bit functions
12.41. Lock Status Register bit functions
12.42. Authentication Status Register bit functions
12.43. Device Type Register bit functions
12.44. Peripheral Identification Registers
12.45. Fields in the Peripheral Identification Registers
12.46. Peripheral ID Register 0 bit functions
12.47. Peripheral ID Register 1 bit functions
12.48. Peripheral ID Register 2 bit functions
12.49. Peripheral ID Register 3 bit functions
12.50. Peripheral ID Register 4 bit functions
12.51. Component Identification Registers
12.52. Processor behavior on debug events
12.53. Values in Link Register after exceptions
12.54. Read PC value after debug state entry
12.55. Permitted updates to the CPSR in debug state
12.56. Accesses to CP15 and CP14 registers in debug state
12.57. Authentication signal restrictions
12.58. Values to write to BCR for a simple breakpoint
12.59. Values to write to WCR for a simple watchpoint
12.60. Example byte address masks for watchpointed objects
13.1. Single-precision three-operand register usage
13.2. Single-precision two-operand register usage
13.3. Double-precision three-operand register usage
13.4. Double-precision two-operand register usage
13.5. NEON and VFP system registers
13.6. Accessing NEON and VFP system registers
13.7. FPSID Register bit functions
13.8. FPSCR Register bit functions
13.9. Vector length and stride combinations
13.10. Floating-Point Exception Register bit functions
13.11. MVFR0 Register bit functions
13.12. MVFR1 Register bit functions
13.13. Default NaN values
13.14. QNaN and SNaN handling
14.1. ETM implementation
14.2. ETM register summary
14.3. ID Register bit functions
14.4. Configuration Code Register bit functions
14.5. Configuration Code Extension Register bit functions
14.6. Peripheral Identification Registers bit functions
14.7. Component Identification Registers bit functions
14.8. Output signals that can be controlled by the Integration Test Registers
14.9. Input signals that can be read by the Integration Test Registers
14.10. ITMISCOUT Register bit functions
14.11. ITMISCIN Register bit functions
14.12. ITTRIGGER Register bit functions
14.13. ITATBDATA0 Register bit functions
14.14. ITATBCTR2 Register bit functions
14.15. ITATBCTR1 Register bit functions
14.16. ITATBCTR0 Register bit functions
14.17. PMU event number mappings
14.18. PMU event cycle mappings
15.1. Trigger inputs
15.2. Trigger outputs
15.3. CTI register summary
15.4. CTI Control Register bit functions
15.5. CTI Interrupt Acknowledge Register bit functions
15.6. CTI Application Trigger Set Register bit functions
15.7. CTI Application Trigger Clear Register bit functions
15.8. CTI Application Pulse Register bit functions
15.9. CTI Trigger to Channel Enable Registers bit functions
15.10. CTI Channel to Trigger Enable Registers bit functions
15.11. CTI Trigger In Status Register bit functions
15.12. CTI Trigger Out Status Register bit functions
15.13. CTI Channel In Status Register bit functions
15.14. CTI Channel Gate Register bit functions
15.15. ASIC Control Register bit functions
15.16. CTI Channel Out Status Register bit functions
15.17. CTI Integration Test Registers
15.18. ITTRIGINACK Register bit functions
15.19. ITCHOUT Register bit functions
15.20. ITTRIGOUT Register bit functions
15.21. ITTRIGOUT connections to other integration test registers
15.22. ITTRIGOUTACK Register bit functions
15.23. ITTRIGOUTACK connections to other integration test registers
15.24. ITCHIN Register bit functions
15.25. ITTRIGIN Register bit functions
15.26. ITTRIGIN connections to other integration test registers
15.27. Authentication Status Register bit functions
15.28. Device ID Register bit functions
15.29. Device Type Identifier Register bit functions
15.30. Peripheral Identification Registers bit functions
15.31. Component Identification Registers bit functions
16.1. Data-processing instructions with a destination
16.2. Data-processing instructions without a destination
16.3. MOV and MOVN instructions
16.4. Multiply instructions
16.5. Parallel arithmetic instructions
16.6. Extended instructions
16.7. Miscellaneous data-processing instructions
16.8. Status register access instructions
16.9. Load instructions
16.10. Store instructions
16.11. Branch instructions
16.12. Nonpipelined CP14 instructions
16.13. Nonpipelined CP15 instructions
16.14. CP15 instructions affected when ACTRL bit[20] = 0
16.15. Dual-issue restrictions
16.16. Memory system effects on instruction timings
16.17. ThumbEE instructions
16.18. Advanced SIMD integer ALU instructions
16.19. Advanced SIMD integer multiply instructions
16.20. Advanced SIMD integer shift instructions
16.21. Advanced SIMD floating-point instructions
16.22. Advanced SIMD byte permute instructions
16.23. Advanced SIMD load/store instructions
16.24. Advanced SIMD register transfer instructions
16.25. VFP Instruction cycle counts
17.1. Format of timing parameter tables
17.2. Timing parameters of AXI interface
17.3. Timing parameters of ATB and CTI interfaces
17.4. Timing parameters of APB interface and miscellaneous debug signals
17.5. Timing parameters of the L1 and L2 MBIST interface
17.6. Timing parameters of the L2 preload interface
17.7. Timing parameters of the DFT interface
17.8. Timing parameters of miscellaneous signals
A.1. AXI interface
A.2. ATB interface
A.3. MBIST interface
A.4. DFT and additional MBIST pin requirements
A.5. Preload engine interface
A.6. APB interface
A.7. Miscellaneous signals
A.8. Miscellaneous debug signals
A.9. Miscellaneous ETM and CTI signals
B.1. Advanced SIMD mnemonics
B.2. VFP data-processing mnemonics
C.1. Differences between issue F and issue G
C.2. Differences between issue G and issue H

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Some material in this document is based on ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic and on IEEE Std. 1500-2005, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A18 July 2006First release for r1p0.
Revision B13 December 2006First release for r1p1.
Revision C13 July 2007First release for r2p0.
Revision D16 November 2007First release for r2p1.
Revision E14 March 2008First release for r2p2.
Revision F06 October 2008First release for r2p3.
Revision G24 October 2008First release for r3p0.
Revision H03 December 2008Second release for r3p0.
Copyright © 2006-2008 ARM Limited. All rights reserved.ARM DDI 0344H
Non-Confidential
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