16.2.11. Coprocessor instructions

The CP15 and CP14 instructions are used to access special-purpose registers that are distributed across the design. They also perform very specialized operations such as cache maintenance. The instructions affected are listed in Table 16.12 and in Table 16.13. The minimum time to complete these CP15 and CP14 operations is 60 cycles. However, the timing of these instructions varies highly. It can take hundreds of cycles, depending on the operation and on the current processor activity.

Table 16.12. Nonpipelined CP14 instructions

InstructionOp1<Rd>CRnCRmOp2
MCR/MRC p140Rdc0-c15c0-c150-7

Table 16.13. Nonpipelined CP15 instructions

InstructionOp1<Rd>CRnCRmOp2Function
MCR p150Rdc1c00Control Register
MCR p150Rdc1c01Auxiliary Control Register
MCR p150Rdc2c00Translation Table Base 0 Register
MCR p150Rdc2c01Translation Table Base 1 Register
MCR p150Rdc2c02Translation Table Base Control Register
MCR p150Rdc3c00Domain Access Control Register
MCR/MRC p150Rdc5c00Data Fault Status Register
MCR/MRC p150Rdc5c01Instruction Fault Status Register
MCR/MRC p150Rdc5c10Data Auxiliary Fault Status Register
MCR/MRC p150Rdc5c11Instruction Auxiliary Fault Status Register
MCR/MRC p150Rdc6c00Data Fault Address Register
MCR/MRC p150Rdc6c01Instruction Fault Address Register
MCR p150Rdc7c51Invalidate I$ Line by MVA to PoU
MCR p150Rdc7c61Invalidate D$ Line by MVA to PoC
MCR p150Rdc7c62Invalidate D$ Line by Set/Way
MCR p150Rdc7c80-3VA-to-PA translation in the Current World
MCR p150Rdc7c84-7VA-to-PA translation in the Other World
MCR p150Rdc7c101Clean D$ Line by MVA to PoC
MCR p150Rdc7c102Clean D$ Line by Set/Way
MCR p150Rdc7c104Data Synchronization Barrier
MCR p150Rdc7c105Data Memory Barrier
MCR p150Rdc7c111Clean D$ Line by MVA to PoU
MCR p150Rdc7c141Clean and Invalidate D$ Line by MVA to PoC
MCR p150Rdc7c142Clean and Invalidate D$ Line by Set/Way
MCR p150Rdc8c50Invalidate I-TLB Unlocked Entries
MCR p150Rdc8c51Invalidate I-TLB Entry by MVA
MCR p150Rdc8c52Invalidate I-TLB Entry on ASID Match
MCR p150Rdc8c60Invalidate D-TLB Unlocked Entries
MCR p150Rdc8c61Invalidate D-TLB Entry by MVA
MCR p150Rdc8c62Invalidate D-TLB Entry on ASID Match
MCR p150Rdc8c70Invalidate Unified-TLB Unlocked Entries
MCR p150Rdc8c71Invalidate Unified-TLB Entry by MVA
MCR p150Rdc8c72Invalidate Unified-TLB Entry on ASID Match
MCR p151Rdc9c00L2$ Lockdown Register
MCR p151Rdc9c02L2$ Auxiliary Control Register
MCR p150Rdc10c00D-TLB Lockdown Register
MCR p150Rdc10c01I-TLB Lockdown Register
MCR p150Rdc10c10D-TLB Preload
MCR p150Rdc10c11I-TLB Preload
MCR p150Rdc10c20Primary Region Remap Register
MCR p150Rdc10c21Normal Memory Remap Register
MCR p150Rdc11c10PLE User Accessibility Register
MCR p150Rdc11c20PLE Channel Number Register
MCR p150Rdc11c30-2PLE Enable Register
MCR p150Rdc11c40PLE Control Register
MCR p150Rdc11c150PLE Context ID Register
MCR p150Rdc13c00FCSE ID Register
MCR p150Rdc13c00Context ID Register
MCR/MRC p15-Rdc15--All Array Access instructions

Table 16.14 shows the CP15 instructions that have improved cycle timing if the Auxiliary Control Register bit[20] = 0,

Table 16.14. CP15 instructions affected when ACTRL bit[20] = 0

InstructionOp1<Rd>CRnCRmOp2Function
MCR p150Rdc7c61Invalidate D$ Line by MVA to PoC
MCR p150Rdc7c62Invalidate D$ Line by Set/Way
MCR p150Rdc7c101Clean D$ Line by MVA to PoC
MCR p150Rdc7c102Clean D$ Line by Set/Way
MCR p150Rdc7c111Clean D$ Line by MVA to PoU
MCR p150Rdc7c141Clean and Invalidate D$ Line by MVA to PoC
MCR p150Rdc7c142Clean and Invalidate D$ Line by Set/Way

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