7.2.6. Instruction cache maintenance

The Cortex-A8 processor is implemented with an optional extension, the IVIPT extension (Instruction cache Virtually Indexed Physically Tagged extension). The effect of this extension is to reduce the instruction cache maintenance requirement to a single condition:

Note

This condition is consistent with the maintenance required for a Virtually Indexed Physically Tagged (VIPT) instruction cache.

Software can read the Cache Type Register to determine whether the IVIPT extension is implemented, see c0, Cache Type Register.

Software written to rely on a VIPT instruction cache must only be used with processors that implement the IVIPT. For maximum compatibility across processors, ARM recommends that operating systems target the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, and do not assume the presence of the IVIPT extension. Software that relies on the IVIPT extension might fail in an unpredictable way on an ARMv7 implementation that does not include the IVIPT extension.

With an instruction cache, the distinction between a VIPT cache and a PIPT cache is much less visible to the programmer than it is for a data cache, because normally the contents of an instruction cache are not changed by writing to the cached memory. However, there are situations where a program must distinguish between the different cache tagging strategies. Example 7.1 describes such a situation.

Example 7.1. A situation where software must be aware of the Instruction cache tagging strategy

Two processes, P1 and P2, share some code and have separate virtual mappings to the same region of instruction memory. P1 changes this region, for example as a result of a JIT, or some other self-modifying code operation. P2 needs to see the modified code.

As part of its self-modifying code operation, P1 must invalidate the changed locations from the instruction cache. If this invalidation is performed by MVA, and the instruction cache is a VIPT cache, then P2 might continue to see the old code. For more information, see the ARM Architecture Reference Manual.

In this situation, if the instruction cache is a VIPT cache, after the code modification the entire instruction cache must be invalidated to ensure P2 observes the new version of the code.


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