3.2.70. c12, Interrupt Status Register

The purpose of the Interrupt Status Register is to:

The Interrupt Status Register is:

Figure 3.63 shows the bit arrangement of the Interrupt Status Register.

Figure 3.63. Interrupt Status Register format

Table 3.140 shows how the bit values correspond with the Interrupt Status Register functions.

Table 3.140. Interrupt Status Register bit functions

[31:9]-Reserved. UNP, SBZ.

Indicates when an external abort is pending:

0 = no abort, reset value

1 = abort pending.


Indicates when an IRQ is pending:

0 = no IRQ, reset value

1 = IRQ pending.


Indicates when an FIQ is pending:

0 = no FIQ, reset value

1 = FIQ pending.

[5:0]-Reserved. UNP, SBZ.

[1] The reset values depend on external signals.


  • The F and I bits directly reflect the state of the nFIQ and nIRQ pins respectively, but are the inverse state.

  • The A bit is set to 1 when an external abort occurs and automatically clears to 0 when the abort is taken.

Table 3.141 shows the results of attempted access for each mode.

Table 3.141. Results of access to the Interrupt Status Register[59]

Secure privilegedNonsecure privilegedSecure UserNonsecure User

[59] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

The A, I, and F bits map to the same format as the CPSR so that you can use the same mask for these bits.

The Monitor can poll these bits to detect the exceptions before it completes context switches. This can reduce interrupt latency.

To access the Interrupt Status Register, read CP15 with:

MRC p15, 0, <Rd>, c12, c1, 0 ; Read Interrupt Status Register
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