3.2.18. c0, Instruction Set Attributes Register 3

The purpose of the Instruction Set Attributes Register 3 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 3 is:

Figure 3.14 shows the bit arrangement of Instruction Set Attributes Register 3.

Figure 3.14. Instruction Set Attributes Register 3 format


Table 3.33 shows how the bit values correspond with the Instruction Set Attributes Register 3 functions.

Table 3.33. Instruction Set Attributes Register 3 bit functions

BitsFieldFunction
[31:28]

Thumb2 executable environment

extension instructions

Indicates support for Thumb2 Executable Environment Extension instructions:

0x1 = Processor supports ENTERX and LEAVEX instructions and modifies the load behavior to include null checking.

[27:24]

NOP

instructions

Indicates support for true NOP instructions:

0x1 = Processor supports true NOP instructions in both the Thumb and ARM instruction sets, and the capability for additional NOP compatible hints.

[23:20]

Thumb copy

instructions

Indicates support for Thumb copy instructions:

0x1 = Processor supports Thumb MOV(3) low register ⇒ low register, and the CPY alias for Thumb MOV(3).

[19:16]

Table branch

instructions

Indicates support for table branch instructions:

0x1 = Processor supports table branch instructions.

[15:12]

Synchronization

primitive

instructions

Indicates support for synchronization primitive instructions.

0x2 = Processor supports:

  • LDREX and STREX

  • LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, and CLREX.

[11:8]

SVC

instructions

Indicates support for SVC instructions:

0x1 = Processor supports SVC.

[7:4]

SIMD

instructions

Indicates support for Single Instruction Multiple Data (SIMD) instructions.

0x3 = Processor supports:

PKHBT, PKHTB, QADD16, QADD8, QADDSUBX, QSUB16, QSUB8, QSUBADDX, SADD16, SADD8, SADDSUBX, SEL, SHADD16, SHADD8, SHADDSUBX, SHSUB16, SHSUB8, SHSUBADDX, SSAT, SSAT16, SSUB16, SSUB8, SSUBADDX, SXTAB16, SXTB16, UADD16, UADD8, UADDSUBX, UHADD16, UHADD8, UHADDSUBX, UHSUB16, UHSUB8, UHSUBADDX, UQADD16, UQADD8, UQADDSUBX, UQSUB16, UQSUB8, UQSUBADDX, USAD8, USADA8, USAT, USAT16, USUB16, USUB8, USUBADDX, UXTAB16, UXTB16, and the GE[3:0] bits in the PSRs.

[3:0]

Saturate

instructions

Indicates support for saturate instructions:

0x1 = Processor supports QADD, QDADD, QDSUB, QSUB and Q flag in PSRs.


Table 3.34 shows the results of attempted access for each mode.

Table 3.34. Results of access to Instruction Set Attributes Register 3[17]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[17] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Instruction Set Attributes Register 3, read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 3 ; Read Instruction Set Attributes Register 3
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