3.2.13. c0, Memory Model Feature Register 2

The purpose of the Memory Model Feature Register 2 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 2 is:

Figure 3.9 shows the bit arrangement of the Memory Model Feature Register 2.

Figure 3.9. Memory Model Feature Register 2 format


Table 3.23 shows how the bit values correspond with the Memory Model Feature Register 2 functions.

Table 3.23. Memory Model Feature Register 2 bit functions

BitsFieldFunction

[31:28]

Hardware access flag

Indicates support for hardware access flag:

0x0 = Processor does not support hardware access flag.

[27:24]

WFI

Indicates support for wait-for-interrupt stalling:

0x1 = Processor supports wait-for-interrupt.

[23:20]

Memory barrier features

Indicates support for memory barrier operations.

0x2 = Processor supports:

  • data synchronization barrier

  • instruction synchronization barrier

  • data memory barrier.

[19:16]

Unified TLB maintenance operations

Indicates support for TLB maintenance operations, unified architecture.

0x0 = Processor does not support:

  • invalidate all entries

  • invalidate TLB entry by MVA

  • invalidate TLB entries by ASID match.

[15:12]

Harvard TLB maintenance operations

Indicates support for TLB maintenance operations, Harvard architecture.

0x2 = Processor supports:

  • invalidate instruction and data TLB, all entries

  • invalidate instruction TLB, all entries

  • invalidate data TLB, all entries

  • invalidate instruction TLB by MVA

  • invalidate data TLB by MVA

  • invalidate instruction and data TLB entries by ASID match

  • invalidate instruction TLB entries by ASID match

  • invalidate data TLB entries by ASID match.

[11:8]

Harvard L1 cache maintenance range operations

Indicates support for cache maintenance range operations, Harvard architecture:

0x0 = no support in processor.

[7:4]

Harvard L1 background prefetch cache range operations

Indicates support for background prefetch cache range operations, Harvard architecture:

0x0 = no support in processor.

[3:0]

Harvard L1 foreground prefetch cache range operations

Indicates support for foreground prefetch cache range operations, Harvard architecture:

0x0 = no support in processor.


Table 3.24 shows the results of attempted access for each mode.

Table 3.24. Results of access to Memory Model Feature Register 2[12]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[12] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Memory Model Feature Register 2, read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 6 ; Read Memory Model Feature Register 2
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